Invention Application
- Patent Title: 3D IC METHOD AND DEVICE
- Patent Title (中): 3D IC方法和设备
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Application No.: PCT/US2006030703Application Date: 2006-08-07
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Publication No.: WO2007021639A3Publication Date: 2009-04-30
- Inventor: ENQUIST PAUL M , FOUNTAIN GAIUS GILLMAN JR , TONG QIN-YI
- Applicant: ZIPTRONIX INC , ENQUIST PAUL M , FOUNTAIN GAIUS GILLMAN JR , TONG QIN-YI
- Assignee: ZIPTRONIX INC,ENQUIST PAUL M,FOUNTAIN GAIUS GILLMAN JR,TONG QIN-YI
- Current Assignee: ZIPTRONIX INC,ENQUIST PAUL M,FOUNTAIN GAIUS GILLMAN JR,TONG QIN-YI
- Priority: US20132105 2005-08-11
- Main IPC: H01L21/4763
- IPC: H01L21/4763
Abstract:
A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.
Information query
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