Invention Application
- Patent Title: COORDINATING ACCESS TO MEMORY LOCATIONS FOR HARDWARE TRANSACTIONAL MEMORY TRANSACTIONS AND SOFTWARE TRANSACTIONAL MEMORY TRANSACTIONS
- Patent Title (中): 协调访问硬件交易记忆交易和软件交易记忆交易的记忆位置
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Application No.: PCT/US2006/046499Application Date: 2006-12-05
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Publication No.: WO2007078538A2Publication Date: 2007-07-12
- Inventor: ADL-TABATABAI, Ali-Reza , SAHA, Bratin , HUDSON, Richard, L. , AKKARY, Haitham , RAJWAR, Ravi
- Applicant: INTEL CORPORATION , ADL-TABATABAI, Ali-Reza , SAHA, Bratin , HUDSON, Richard, L. , AKKARY, Haitham , RAJWAR, Ravi
- Applicant Address: 2200 Mission College Boulevard, Santa Clara, CA 95052 US
- Assignee: INTEL CORPORATION,ADL-TABATABAI, Ali-Reza,SAHA, Bratin,HUDSON, Richard, L.,AKKARY, Haitham,RAJWAR, Ravi
- Current Assignee: INTEL CORPORATION,ADL-TABATABAI, Ali-Reza,SAHA, Bratin,HUDSON, Richard, L.,AKKARY, Haitham,RAJWAR, Ravi
- Current Assignee Address: 2200 Mission College Boulevard, Santa Clara, CA 95052 US
- Agency: VICTOR, David, W. et al.
- Priority: US11/303,529 20051215
- Main IPC: G06F9/46
- IPC: G06F9/46
Abstract:
Provided is a method, system, and program for coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions. A hardware transaction executing in hardware transactional memory initiates a request to access a memory location. A fault is returned to the hardware transaction request in response to an operation by one software transaction executing in a software transactional memory.
Information query
