Invention Application
- Patent Title: MULTIPLIER
- Patent Title (中): 乘数
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Application No.: PCT/US2006/048417Application Date: 2006-12-18
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Publication No.: WO2007078939A2Publication Date: 2007-07-12
- Inventor: FEGHALI, Wajdi, K. , HASENPLAUGH, William, C. , WOLRICH, Gilbert, M. , CUTTER, Daniel, F. , GOPAL, Vinodh , GAUBATZ, Gunnar
- Applicant: INTEL CORPORATION , FEGHALI, Wajdi, K. , HASENPLAUGH, William, C. , WOLRICH, Gilbert, M. , CUTTER, Daniel, F. , GOPAL, Vinodh , GAUBATZ, Gunnar
- Applicant Address: 2200 Mission College Boulevard, Santa Clara, CA 95052 US
- Assignee: INTEL CORPORATION,FEGHALI, Wajdi, K.,HASENPLAUGH, William, C.,WOLRICH, Gilbert, M.,CUTTER, Daniel, F.,GOPAL, Vinodh,GAUBATZ, Gunnar
- Current Assignee: INTEL CORPORATION,FEGHALI, Wajdi, K.,HASENPLAUGH, William, C.,WOLRICH, Gilbert, M.,CUTTER, Daniel, F.,GOPAL, Vinodh,GAUBATZ, Gunnar
- Current Assignee Address: 2200 Mission College Boulevard, Santa Clara, CA 95052 US
- Agency: VINCENT, Lester, J. et al.
- Priority: US11/323,994 20051230
- Main IPC: G06F7/525
- IPC: G06F7/525
Abstract:
In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
Information query
IPC分类: