公开(公告)号：WO2022256293A1

公开(公告)日：2022-12-08

申请号：PCT/US2022/031527

申请日：2022-05-31

Applicant: CEREMORPHIC, INC

Inventor： KRAEMER, Martin ,  BOESCH, Ryan ,  XIONG, Wei

IPC: G06F7/523 ,  G06F7/525 ,  G06F7/53 ,  H03M1/66

Abstract: An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor to form an analog multiplication product as a charge applied to the differential charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

公开(公告)号：WO2007078939A2

公开(公告)日：2007-07-12

申请号：PCT/US2006/048417

申请日：2006-12-18

Applicant: INTEL CORPORATION ,  FEGHALI, Wajdi, K. ,  HASENPLAUGH, William, C. ,  WOLRICH, Gilbert, M. ,  CUTTER, Daniel, F. ,  GOPAL, Vinodh ,  GAUBATZ, Gunnar

Inventor： FEGHALI, Wajdi, K. ,  HASENPLAUGH, William, C. ,  WOLRICH, Gilbert, M. ,  CUTTER, Daniel, F. ,  GOPAL, Vinodh ,  GAUBATZ, Gunnar

IPC: G06F7/525

CPC classification number: G06F7/5275

Abstract: In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.

Abstract translation: 一般来说，在一个方面，本发明描述了一种乘法器，其包括并行配置的一组多个乘法器，其中多个乘法器的集合具有对第一操作数的访问和第二操作数的乘法，第一操作数具有多个段，第二操作数具有多个段 具有多个段的操作数。 所述乘法器还包括逻辑以将所述第二操作数的单个段重复地提供给所述多个乘法器集合的每个乘法器，并且将所述第一操作数的多个相应段提供给所述多个乘法器组中的各个乘法器，直到所述第二 操作数已被提供给第一个操作数的每个段。 该逻辑至少部分地基于第一操作数内的相应段的位置来移动多个乘法器组中不同的乘法器的输出。 乘法器还包括耦合到逻辑的累加器。

公开(公告)号：WO2013044276A1

公开(公告)日：2013-04-04

申请号：PCT/AT2011/000397

申请日：2011-09-27

Applicant: TECHNISCHE UNIVERSITÄT GRAZ ,  HUTTER, Michael ,  WENGER, Erich

Inventor： HUTTER, Michael ,  WENGER, Erich

IPC: G06F7/525

CPC classification number: G06F7/525

Abstract: To multiply two multi-word operands, a number e of caching registers is used to cache the values of operand words. The multiplication is done using several runs, which each com¬ prise several parts (R0Q1, R0Q2, R1Q4). In an initial part (R0Q1, R1Q1) words of the operands are loaded into caching registers, and a first set of partial products are processed; the initial part leaves a number e of words of a first operand in caching registers. Because of the cached words of one operand, a sequential inner part (R0Q2, R1Q2; R0Q3, R1Q3) re-uses cached operand words without requiring load operations for that operand, and only words of the other operand are loaded for processing of partial products, preferably according to a product-scanning multiplication method, namely, by grouping together operations for partial products of the same product index (k); each inner part again leaves a number of operand words in caching registers, though of the respective other operand. A final part (R0Q4, R1Q4) processed a final set of partial products using cached operand words.

Abstract translation: 要乘以两个多字操作数，使用数个缓存寄存器来缓存操作数字的值。 乘法是使用几个运行完成的，每个运行都会包含几个部分（R0Q1，R0Q2，R1Q4）。 在初始部分（R0Q1，R1Q1）中，操作数的字被加载到高速缓存寄存器中，第一组部分乘积被处理; 初始部分在缓存寄存器中留下第一个操作数的数字e。 由于一个操作数的缓存字，顺序内部部分（R0Q2，R1Q2; R0Q3，R1Q3）重新使用高速缓存的操作数字，而不需要对该操作数进行加载操作，只有加载其他操作数的字才能处理部分产品 优选地根据乘积扫描乘法方法，即通过将相同乘积索引（k）的部分乘积分组在一起; 每个内部部分在缓存寄存器中再次留下多个操作数字，尽管各自的其他操作数。 最后一部分（R0Q4，R1Q4）使用缓存的操作数字处理最终的部分产品集。

公开(公告)号：WO2008120001A1

公开(公告)日：2008-10-09

申请号：PCT/GB2008/001167

申请日：2008-04-02

Applicant: ASPEX SEMICONDUCTOR LIMITED ,  WHITAKER, Martin ,  JALOWIECKI, Ian

Inventor： WHITAKER, Martin ,  JALOWIECKI, Ian

IPC: G06F15/80 ,  G06F7/533 ,  G06F7/525

CPC classification number: G06F7/5338 ,  G06F7/525

Abstract: A processing element of a Single Instruction Multiple Data parallel processing array processor is described where the processing element is configured to implement two bits at-a-time arithmetic operations local to the processing element. The processing element comprises: a plurality of operand registers arranged to store operands and results for arithmetic operations; an arithmetic logic unit for effecting the two bits at-a-time logical arithmetic operations including a Booth's algorithm mathematical operation, where subgroups of a multiplier are used to determine multiples (summands) of an operand to be summed together to determine the multiplication result; and variation means for enabling local conditional variation of the mathematical operation; the variation means comprising a Booth's algorithm delay register which provides the least significant bit of a current multiplier subgroup, the register being arranged to read the most significant bit of the current subgroup and to use this as the least significant bit of the next subgroup for the next summand determination operation.

Abstract translation: 描述了单指令多数据并行处理阵列处理器的处理元件，其中处理元件被配置为实现处理元件本地的每次算术运算两个比特。 处理元件包括：多个操作数寄存器，被布置为存储用于算术运算的操作数和结果; 算术逻辑单元，用于每次实时地进行包括布斯算法运算的逻辑算术运算的两个比特，其中乘法器的子组用于确定要求和在一起以确定乘法结果的操作数的倍数（加法）; 以及用于使得数学运算的局部条件变化的变化装置; 所述变化装置包括布斯算法延迟寄存器，其提供当前乘法器子组的最低有效位，所述寄存器被布置为读取当前子组的最高有效位，并将其用作下一个子组的最低有效位，用于 下一个求和确定操作。

公开(公告)号：WO2007078939A3

公开(公告)日：2007-11-15

申请号：PCT/US2006048417

申请日：2006-12-18

Applicant: INTEL CORP ,  FEGHALI WAJDI K ,  HASENPLAUGH WILLIAM C ,  WOLRICH GILBERT M ,  CUTTER DANIEL F ,  GOPAL VINODH ,  GAUBATZ GUNNAR

Inventor： FEGHALI WAJDI K ,  HASENPLAUGH WILLIAM C ,  WOLRICH GILBERT M ,  CUTTER DANIEL F ,  GOPAL VINODH ,  GAUBATZ GUNNAR

IPC: G06F7/525

CPC classification number: G06F7/5275

Abstract: In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.

Abstract translation: 通常，在一个方面，本公开描述了一种乘法器，该乘法器包括并行配置的一组多个乘法器，其中多个乘法器的集合可以访问第一操作数和第二操作数以便相乘，第一操作数具有多个段并且第二操作数 操作数有多个段。 乘法器还包括逻辑，用于重复提供第二操作数的单个段到该组多个乘法器中的每个乘法器，并且将第一操作数的多个相应段提供给该多个乘法器集中的相应乘法直到第二个 操作数已经与第一个操作数的每个段一起提供。 该逻辑至少部分地基于第一操作数内的各个段的位置来移位该多个乘法器组中的不同者的输出。 乘法器还包括一个连接到逻辑的累加器。