Invention Application
- Patent Title: DYNAMICALLY CONFIGURABLE LOGIC GATE USING A NONLINEAR ELEMENT
- Patent Title (中): 使用非线性元素的动态配置逻辑门
-
Application No.: PCT/US2007/088356Application Date: 2007-12-20
-
Publication No.: WO2008079964A1Publication Date: 2008-07-03
- Inventor: KIEL, Steven, Lee , KRENING, Douglas, Norman , LEHMAN, Lark, Edward , SCHNEIDERWIND, Michael, Joseph
- Applicant: CHAOLOGIX, INC. , KIEL, Steven, Lee , KRENING, Douglas, Norman , LEHMAN, Lark, Edward , SCHNEIDERWIND, Michael, Joseph
- Applicant Address: 101 SE 2nd Place Gainesville, FL 32601 US
- Assignee: CHAOLOGIX, INC.,KIEL, Steven, Lee,KRENING, Douglas, Norman,LEHMAN, Lark, Edward,SCHNEIDERWIND, Michael, Joseph
- Current Assignee: CHAOLOGIX, INC.,KIEL, Steven, Lee,KRENING, Douglas, Norman,LEHMAN, Lark, Edward,SCHNEIDERWIND, Michael, Joseph
- Current Assignee Address: 101 SE 2nd Place Gainesville, FL 32601 US
- Agency: GIBBONS, Jon, A. et al.
- Priority: US11/615,382 20061222
- Main IPC: G06F7/57
- IPC: G06F7/57
Abstract:
A dynamically configurable logic gate includes an input summer for receiving a first input signal and a second input signal to generate a summed input signal. Further the dynamically configurable logic gate includes a nonlinear element that applies a nonlinear function to the summed input signal to produce a nonlinear output signal. The dynamically configurable logic gate output signal corresponds to one of a plurality of different logic gates responsive to adjusting the summed input signal and/or the nonlinear function. In another embodiment, the dynamically configurable logic gate includes feedback to one of the inputs. The dynamically configurable logic gate receives the two inputs and operates as one of a plurality of different logic gate types so as to produce an output signal that corresponds to a memory latch according to a selection of the control signal. An array structure of dynamically configurable logic elements is also disclosed.
Information query