Invention Application
- Patent Title: GEOMETRY OF MOS DEVICE WITH LOW ON-RESISTANCE
- Patent Title (中): 具有低电阻性的MOS器件的几何
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Application No.: PCT/US2007088866Application Date: 2007-12-26
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Publication No.: WO2008083180A3Publication Date: 2008-08-28
- Inventor: SUTARDJA SEHAT , KRISHNAMOORTHY RAVISHANKER
- Applicant: MARVELL WORLD TRADE LTD , SUTARDJA SEHAT , KRISHNAMOORTHY RAVISHANKER
- Assignee: MARVELL WORLD TRADE LTD,SUTARDJA SEHAT,KRISHNAMOORTHY RAVISHANKER
- Current Assignee: MARVELL WORLD TRADE LTD,SUTARDJA SEHAT,KRISHNAMOORTHY RAVISHANKER
- Priority: US88225006 2006-12-28
- Main IPC: H01L27/06
- IPC: H01L27/06
Abstract:
A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region surrounding the drain region, source regions arranged around the gate region and across from the drain region, and bulk regions arranged around the gate region and separating the source regions. The gate region is formed in a loop around the drain region. In this manner, the on-resistance (Ron) of a MOS device is decreased without also increasing the area of the MOS device.
Information query
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