A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems Some structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and nsky switch to alternative technologies Some structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced oVT compared to conventional bulk CMOS and can allow the threshold voltage VT ofFETs having dopants in the channel region to be set more precisely The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors There are many ways to configure the DDC to achieve different benefits