公开(公告)号：WO2011062789A1

公开(公告)日：2011-05-26

申请号：PCT/US2010/055762

申请日：2010-11-08

Applicant: SUVOLTA, INC. ,  THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

Inventor： THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

IPC: H01L29/02

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66636 ,  H01L29/7834

Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sigma VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors

Abstract translation: 提供了一套新颖的结构和方法来减少广泛的电子设备和系统的功耗。这些结构和方法中的一些可以通过重用现有的大量CMOS工艺流程和制造技术来实现，这允许半导体工业以及 更广泛的电子工业，以避免成本高昂的风险转换到替代技术如将讨论的，一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体积相比具有降低的sigma VT CMOS，并且可以允许在沟道区域中具有掺杂剂的FET的阈值电压VT被更精确地设置。与常规体CMOS晶体管相比，DDC设计还可以具有强的体效应，这可以允许对功率消耗的显着动态控制 DDC晶体管

公开(公告)号：WO2008134688A1

公开(公告)日：2008-11-06

申请号：PCT/US2008/061946

申请日：2008-04-30

Applicant: DSM SOLUTIONS, INC. ,  THUMMALAPALLY, Damodar, R.

Inventor： THUMMALAPALLY, Damodar, R.

IPC: H01L27/098 ,  H01L27/108 ,  G11C11/403 ,  G11C15/04

CPC classification number: H01L27/108 ,  G11C15/043 ,  H01L27/098 ,  H01L29/808

Abstract: A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) used to form a content addressable memory (CAM) cell is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. The data storage region provides a first threshold voltage to the JFET when storing a first data value and provides a second threshold voltage to the JFET when storing a second data value. The memory cell is a dynamic random access memory (DRAM) cell and can be used to form a CAM cell. The CAM cell may be a ternary CAM cell formed with as few as two JFETs.

Abstract translation: 公开了一种包括具有用于形成内容寻址存储器（CAM）单元的结型场效应晶体管（JFET）的存储单元的半导体器件。 JFET可以包括设置在第一和第二绝缘区域之间的数据存储区域。 当存储第一数据值时，数据存储区域向JFET提供第一阈值电压，并且当存储第二数据值时，向JFET提供第二阈值电压。 存储单元是动态随机存取存储器（DRAM）单元，可用于形成CAM单元。 CAM单元可以是形成有至少两个JFET的三元CAM单元。

公开(公告)号：WO2008028012A1

公开(公告)日：2008-03-06

申请号：PCT/US2007/077190

申请日：2007-08-30

Applicant: DSM SOLUTIONS INC. ,  CHOU, Richard, K. ,  THUMMALAPALLY, Damodar, R.

Inventor： CHOU, Richard, K. ,  THUMMALAPALLY, Damodar, R.

IPC: H03K19/0185

CPC classification number: H03K19/018521 ,  H03K3/356034

Abstract: A level shifting circuit can include a first input junction field effect transistor (JFET) having a gate coupled to receive an input signal having a first voltage swing that provides a controllable impedance path between a first supply node and a first terminal of a first bias stack including at least one JFET. A driver circuit can be coupled to receive an output from the first bias stack that provides a level shifted output having a second voltage swing that is less than the first voltage swing.

Abstract translation: 电平移位电路可以包括第一输入结场效应晶体管（JFET），其具有被耦合以接收具有第一电压摆幅的输入信号的栅极，所述第一电压摆幅在第一供电节点和第一偏置堆叠的第一端子之间提供可控阻抗路径 包括至少一个JFET。 驱动器电路可以被耦合以接收来自第一偏置堆叠的输出，其提供具有小于第一电压摆幅的第二电压摆幅的电平偏移输出。

公开(公告)号：WO2011103318A1

公开(公告)日：2011-08-25

申请号：PCT/US2011/025284

申请日：2011-02-17

Applicant: SUVOLTA, INC. ,  THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

Inventor： THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

IPC: H01L29/76

CPC classification number: H01L29/1083 ,  H01L21/0262 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/0921 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1079 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7838

Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced aV'r compared to conventional bulk CMOS and can allow the threshold voltage V T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors.

Abstract translation: 提供了一套新颖的结构和方法，以减少广泛的电子设备和系统的功耗。 这些结构和方法中的一些可以通过重用现有的大量CMOS工艺流程和制造技术来实现，从而允许半导体行业以及更广泛的电子行业避免代替替代技术的成本高昂的风险。 如将要讨论的那样，一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的aV'，并且可以允许具有掺杂剂的FET的阈值电压VT 要更精确地设置通道区域。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。

公开(公告)号：WO2011041110A1

公开(公告)日：2011-04-07

申请号：PCT/US2010/049000

申请日：2010-09-15

Applicant: SUVOLTA, INC. ,  THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

Inventor： THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

IPC: H01L21/335

CPC classification number: H01L21/823412 ,  H01L21/823493 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/105 ,  H01L29/1079 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834

Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems Some structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and nsky switch to alternative technologies Some structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced oVT compared to conventional bulk CMOS and can allow the threshold voltage VT ofFETs having dopants in the channel region to be set more precisely The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors There are many ways to configure the DDC to achieve different benefits

Abstract translation: 提供了一套新颖的结构和方法，以减少广泛的电子设备和系统的功耗。一些结构和方法可以通过重用现有的大容量CMOS工艺流程和制造技术来实现，从而允许半导体工业以及更广泛的 电子工业，以避免昂贵的和非法的转换到替代技术一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有降低的oVT，并且可以允许FET的阈值电压VT具有 沟道区域中的掺杂剂要更精确地设置DDC设计与常规体CMOS晶体管相比可以具有强大的机体效应，这可以使DDC晶体管的功耗显着动态控制有很多种配置DDC的方法可以实现 不同的好处

公开(公告)号：WO2009020787A1

公开(公告)日：2009-02-12

申请号：PCT/US2008/071338

申请日：2008-07-28

Applicant: DSM SOLUTIONS, INC. ,  THUMMALAPALLY, Damodar, R. ,  RAY, Abhijit

Inventor： THUMMALAPALLY, Damodar, R. ,  RAY, Abhijit

IPC: H01L27/098 ,  H01L27/118 ,  H03K19/177

CPC classification number: H01L27/11803 ,  H01L27/098 ,  H01L29/808 ,  H03K19/17736 ,  H03K19/1778

Abstract: A switching circuit (100) comprises a plurality of first signal (106-0) lines of a programmable logic device, a plurality of second signal lines (106-1) of the programmable logic device, and a plurality of switch elements (104-0, 104-1)-. Each switch element couples one first signal line to a second signal line and includes one or more switch junction field effect transistors (JFETs (108, 110) having a first control gate (108-0, 110-0) separated from a second control gate (108-3, 110-3) by a channel region.

Abstract translation: 开关电路（100）包括可编程逻辑器件的多个第一信号（106-0）线，可编程逻辑器件的多个第二信号线（106-1）和多个开关元件（104- 0，104-1） - 。 每个开关元件将一个第一信号线耦合到第二信号线并且包括一个或多个开关结场效应晶体管（JFET（108,110），其具有与第二控制栅极分离的第一控制栅极（108-0,110-0） （108-3,110-3）。

公开(公告)号：WO2011103314A1

公开(公告)日：2011-08-25

申请号：PCT/US2011/025278

申请日：2011-02-17

Applicant: SUVOLTA, INC. ,  THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

Inventor： THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

IPC: H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/10 ,  H01L29/786 ,  H01L27/11

CPC classification number: H01L29/1083 ,  H01L21/0262 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/0921 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1079 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7838

Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV T compared to conventional bulk CMOS and can allow the threshold voltage V T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. There are many ways to configure the DDC to achieve different benefits, and additional structures and methods presented herein can be used alone or in conjunction with the DDC to yield additional benefits.

Abstract translation: 提供了一套新颖的结构和方法，以减少广泛的电子设备和系统的功耗。 这些结构和方法中的一些可以通过重用现有的大量CMOS工艺流程和制造技术来实现，从而允许半导体行业以及更广泛的电子行业避免代替替代技术的成本高昂的风险。 如将要讨论的那样，一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的sVT，并且可以允许在沟道中具有掺杂剂的FET的阈值电压VT 区域要更精确地设置。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 配置DDC以实现不同的好处有许多方法，本文中提供的其他结构和方法可以单独使用或与DDC结合使用，以产生额外的好处。

公开(公告)号：WO2011062788A1

公开(公告)日：2011-05-26

申请号：PCT/US2010/055760

申请日：2010-11-08

Applicant: SUVOLTA, INC. ,  THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

Inventor： THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

IPC: H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/10 ,  H01L29/786 ,  H01L27/11

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66636 ,  H01L29/7834

Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV T compared to conventional bulk CMOS and can allow the threshold voltage V T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. There are many ways to configure the DDC to achieve different benefits, and additional structures and methods presented herein can be used alone or in conjunction with the DDC to yield additional benefits.

Abstract translation: 提供了一套新颖的结构和方法，以减少广泛的电子设备和系统的功耗。 这些结构和方法中的一些可以通过重用现有的大量CMOS工艺流程和制造技术来实现，从而允许半导体行业以及更广泛的电子行业避免代替替代技术的成本高昂的风险。 如将要讨论的那样，一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的sVT，并且可以允许在沟道区域中具有掺杂剂的FET的阈值电压VT 要更精确地设置。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 配置DDC以实现不同的好处有许多方法，本文中提供的其他结构和方法可以单独使用或与DDC结合使用，以产生额外的好处。

公开(公告)号：WO2008137441A3

公开(公告)日：2008-12-31

申请号：PCT/US2008061944

申请日：2008-04-30

Applicant: DSM SOLUTIONS INC ,  THUMMALAPALLY DAMODAR R

Inventor： THUMMALAPALLY DAMODAR R

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10897 ,  G11C11/404 ,  H01L27/108

Abstract: A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. The data storage region provides a first threshold voltage to the JFET when storing a first data value and provides a second threshold voltage to the JFET when storing a second data value. The memory cell is a dynamic random access memory (DRAM) cell.

Abstract translation: 公开了包括具有结型场效应晶体管（JFET）的存储器单元的半导体器件。 JFET可以包括设置在第一和第二绝缘区域之间的数据存储区域。 数据存储区在存储第一数据值时向JFET提供第一阈值电压，并且当存储第二数据值时向JFET提供第二阈值电压。 存储器单元是动态随机存取存储器（DRAM）单元。

公开(公告)号：WO2008042566A3

公开(公告)日：2008-06-26

申请号：PCT/US2007078216

申请日：2007-09-12

Applicant: DSM SOLUTIONS INC ,  KAPOOR ASHOK KUMAR ,  CHOU RICHARD K ,  THUMMALAPALLY DAMODAR R

Inventor： KAPOOR ASHOK KUMAR ,  CHOU RICHARD K ,  THUMMALAPALLY DAMODAR R

IPC: H01L27/02 ,  H01L21/336 ,  H01L21/337 ,  H01L29/10 ,  H01L29/808

CPC classification number: H01L27/0207 ,  H01L29/1041 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/808 ,  H01L29/8086 ,  H03K19/09403

Abstract: A semiconductor device includes a first circuit section (200A) having at least one transistor (Tl) coupled to at least three conductive lines (202, 204, 206) formed from a conductive layer. No more than one of the at least one of the three conductive lines (204) forms a control terminal of the at least one transistor. In addition, a second circuit section (200B) includes at least two transistors (T3 - T6). Each such transistor has a control terminal (234, 236, 238, 240) formed by a conductive line formed from the same conductive layer. The three conductive lines of the first circuit section have the same pitch pattern as the conductive lines of the second circuit section.

Abstract translation: 半导体器件包括具有耦合到由导电层形成的至少三个导电线（202,204,206）的至少一个晶体管（T1）的第一电路部分（200A）。 三条导线（204）中的至少一条导线中的至少一条形成至少一个晶体管的控制端。 此外，第二电路部分（200B）包括至少两个晶体管（T3-T6）。 每个这样的晶体管具有由由相同的导电层形成的导电线形成的控制端子（234,236,238,240）。 第一电路部分的三条导线与第二电路部分的导线具有相同的间距图形。