发明申请
- 专利标题： LOW POWER COMPLEMENTARY LOGIC LATCH AND RF DIVIDER
- 专利标题（中）： 低功率补充逻辑锁和射频分频器
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申请号： PCT/US2010/059577申请日： 2010-12-08
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公开(公告)号： WO2011072081A1公开(公告)日： 2011-06-16
- 发明人: SOLTANIAN, Babak , SAVOJ, Jafar
- 申请人： QUALCOMM INCORPORATED , SOLTANIAN, Babak , SAVOJ, Jafar
- 申请人地址： Attn: International Ip Administration 5775 Morehouse Drive San Diego, California 92121 US
- 专利权人： QUALCOMM INCORPORATED,SOLTANIAN, Babak,SAVOJ, Jafar
- 当前专利权人： QUALCOMM INCORPORATED,SOLTANIAN, Babak,SAVOJ, Jafar
- 当前专利权人地址： Attn: International Ip Administration 5775 Morehouse Drive San Diego, California 92121 US
- 代理机构： XU, Jiayu
- 优先权： US12/633,281 20091208
- 主分类号： H03K3/356
- IPC分类号： H03K3/356
摘要：
A quadrature output (IP, IN, QP, QN) high-frequency RF divide-by-two circuit (129) includes a pair of differential complementary logic latches (142, 143). The latches are interconnected to form a toggle flip-flop (200). Each latch (200) includes a tracking cell and a locking cell. In a first embodiment (200), the locking cell includes two complementary logic inverters (201, 205, 203, 207) and two transmission gates (202, 206; 204, 208). When the locking cell is locked, the two gates (211, 213; 212, 214) are enabled such that the locked (i.e., latched) signal passes through both transmission gates and both inverters. In one advantageous aspect, the tracking cell only involves two transmission gates (211, 213; 212, 214). Due to the circuit topology, the first embodiment is operable from a low supply voltage at a high operating frequency while consuming a low amount of supply current. In a second (300) and third embodiment (400), the tracking cell involves a pair of inverters ((301, 304; 302, 305) or (401, 404; 402, 405)). The sources of the transistors of the inverters are, however, coupled together thereby resulting in performance advantages over conventional circuits.
IPC分类:
