公开(公告)号：WO2007127861A3

公开(公告)日：2008-07-17

申请号：PCT/US2007067536

申请日：2007-04-26

Applicant: RAMBUS INC ,  UNIV LELAND STANFORD JUNIOR ,  ABBASFAR ALIAZAM ,  AMIRKHANY AMIR ,  SAVOJ JAFAR

Inventor： ABBASFAR ALIAZAM ,  AMIRKHANY AMIR ,  SAVOJ JAFAR

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: In a method of characterizing a circuit, a test sequence is provided A response of the circuit to the test sequence is determined A transfer function that corresponds to the response is determined The transfer function is decomposed into a plurality of terms A respective term corresponds to an nth-order term in an expansion of at least 3rd order that corresponds to the transfer function A characteristic associated with the circuit is simulated using at least one of the terms in the plurality of terms Figure 1 is a block diagram illustrating an embodiment of a system.

Abstract translation: 在表征电路的方法中，提供测试序列确定电路对测试序列的响应确定对应于响应的传递函数。传递函数被分解成多个术语A相应的术语对应于 对应于传递函数的至少3阶扩展的n阶项被使用多个术语中的术语中的至少一个来模拟使用与电路相关联的特性图1是示出系统的实施例的框图 。

公开(公告)号：WO2012129553A1

公开(公告)日：2012-09-27

申请号：PCT/US2012/030474

申请日：2012-03-23

Applicant: QUALCOMM INCORPORATED ,  TAGHIVAND, Mazhareddin ,  SAVOJ, Jafar ,  CHEN, Mingdeng

Inventor： TAGHIVAND, Mazhareddin ,  SAVOJ, Jafar ,  CHEN, Mingdeng

IPC: H03K3/356 ,  H03K23/42

CPC classification number: H03K3/356182 ,  H03B19/14 ,  H03K23/425

Abstract: A frequency divider circuit is described. The frequency divider circuit (602) includes a first cross - coupling (606a). The first cross - coupling (606a) includes a first cross - coupled transistor (650a) with a first gate (608a). The first gate is separately biased. The first cross - coupling also includes a second cross - coupled transistor (650b) with a second gate (608b). The second gate is separately biased. The first gate (608a) is coupled to the second cross - coupled transistor (650b) and the second gate (608b) is coupled to the first cross - coupled transistor (650a).

Abstract translation: 描述了分频器电路。 分频器电路（602）包括第一交叉耦合（606a）。 第一交叉耦合（606a）包括具有第一栅极（608a）的第一交叉耦合晶体管（650a）。 第一个门是单独的偏见。 第一交叉耦合还包括具有第二栅极（608b）的第二交叉耦合晶体管（650b）。 第二个门是分开的偏见。 第一栅极（608a）耦合到第二交叉耦合晶体管（650b），第二栅极（608b）耦合到第一交叉耦合晶体管（650a）。

公开(公告)号：WO2011049986A1

公开(公告)日：2011-04-28

申请号：PCT/US2010/053254

申请日：2010-10-19

Applicant: QUALCOMM Incorporated ,  SAVOJ, Jafar

Inventor： SAVOJ, Jafar

IPC: H03H7/21

CPC classification number: H03H7/21 ,  H03H2007/0192

Abstract: An LR polyphase filter (410) implemented with inductors (422, 428) and resistors (424, 426) includes first and second paths, with each path including an inductor coupled to a resistor. The first and second paths receive a first input signal (Vin) and provide first and second output signals (Vout1,Vout2), respectively, which may be in quadrature. For a differential design, the polyphase filter (430) further includes third and fourth paths, which receive a second input signal and provide third and fourth output signals, respectively. The four output signals may be 90 out of phase. The first and second input signals are for a differential input signal. The first and third output signals are for a first differential output signal, and the second and fourth output signals are for a second differential output signal. Each inductor may be implemented with a transmission line.

Abstract translation: 用电感器（422,428）和电阻器（424,426）实现的LR多相滤波器（410）包括第一和第二路径，每个路径包括耦合到电阻器的电感器。 第一和第二路径接收第一输入信号（Vin）并且分别提供可以是正交的第一和第二输出信号（Vout1，Vout2）。 对于差分设计，多相滤波器（430）还包括第三和第四路径，其分别接收第二输入信号并提供第三和第四输出信号。 四个输出信号可以是90°异相。 第一和第二输入信号用于差分输入信号。 第一和第三输出信号用于第一差分输出信号，第二和第四输出信号用于第二差分输出信号。 每个电感器可以用传输线来实现。

公开(公告)号：WO2011003040A1

公开(公告)日：2011-01-06

申请号：PCT/US2010/040843

申请日：2010-07-01

Applicant: QUALCOMM INCORPORATED ,  PARK, Dongmin ,  SAVOJ, Jafar

Inventor： PARK, Dongmin ,  SAVOJ, Jafar

IPC: H03L7/24 ,  H03B27/00 ,  H03D7/16

CPC classification number: H03L7/24 ,  H03B5/1215 ,  H03B5/1228 ,  H03B19/14 ,  H03B27/00 ,  H03B2200/007 ,  H03B2200/0074 ,  H03B2200/0078 ,  H03B2200/0082

Abstract: A local oscillator communicates a signal of relatively low frequency across an integrated circuit to the location of a mixer. Near the mixer, a frequency-multiplying SubHarmonically Injection-Locked Oscillator (SHILO) receives the signal and generates therefrom a higher frequency signal. If the SHILO outputs I and Q quadrature signals, then the I and Q signals drive the mixer. If the SHILO does not generate quadrature signals, then a quadrature generating circuit receives the SHILO output signal and generates therefrom I and Q signals that drive the mixer. In one advantageous aspect, the frequency of the signal communicated over distance from the local oscillator to the SHILO is lower than the frequency of the I and Q signals that drive the mixer locally. Reducing the frequency of the signal communicated over distance can reduce power consumption of the LO signal distribution system by more than fifty percent as compared to conventional systems.

Abstract translation: 本地振荡器将跨越集成电路的相对较低频率的信号传送到混频器的位置。 在混频器附近，倍频次谐波注入锁定振荡器（SHILO）接收信号并从中产生较高频率的信号。 如果SHILO输出I和Q正交信号，则I和Q信号驱动混频器。 如果SHILO不产生正交信号，则正交发生电路接收SHILO输出信号并从其产生驱动混频器的I和Q信号。 在一个有利的方面，从本地振荡器到SHILO的距离传递的信号的频率低于驱动混频器的本地I和Q信号的频率。 与常规系统相比，降低信号传输距离的频率可以将LO信号分配系统的功耗降低50％以上。

公开(公告)号：WO2011072081A1

公开(公告)日：2011-06-16

申请号：PCT/US2010/059577

申请日：2010-12-08

Applicant: QUALCOMM INCORPORATED ,  SOLTANIAN, Babak ,  SAVOJ, Jafar

Inventor： SOLTANIAN, Babak ,  SAVOJ, Jafar

IPC: H03K3/356

CPC classification number: H03K3/356156 ,  H03K3/356121

Abstract: A quadrature output (IP, IN, QP, QN) high-frequency RF divide-by-two circuit (129) includes a pair of differential complementary logic latches (142, 143). The latches are interconnected to form a toggle flip-flop (200). Each latch (200) includes a tracking cell and a locking cell. In a first embodiment (200), the locking cell includes two complementary logic inverters (201, 205, 203, 207) and two transmission gates (202, 206; 204, 208). When the locking cell is locked, the two gates (211, 213; 212, 214) are enabled such that the locked (i.e., latched) signal passes through both transmission gates and both inverters. In one advantageous aspect, the tracking cell only involves two transmission gates (211, 213; 212, 214). Due to the circuit topology, the first embodiment is operable from a low supply voltage at a high operating frequency while consuming a low amount of supply current. In a second (300) and third embodiment (400), the tracking cell involves a pair of inverters ((301, 304; 302, 305) or (401, 404; 402, 405)). The sources of the transistors of the inverters are, however, coupled together thereby resulting in performance advantages over conventional circuits.

Abstract translation: 正交输出（IP，IN，QP，QN）高频RF分频电路（129）包括一对差分互补逻辑锁存器（142,143）。 锁存器互连以形成切换触发器（200）。 每个锁存器（200）包括跟踪单元和锁定单元。 在第一实施例（200）中，锁定单元包括两个互补逻辑反相器（201,205,203,207）和两个传输门（202,206; 204,208）。 当锁定单元被锁定时，两个门（211,213,212,214）被使能使得锁定（即锁存的）信号通过两个传输门和两个逆变器。 在一个有利的方面，跟踪单元仅涉及两个传输门（211,213; 212,214）。 由于电路拓扑结构，第一实施例可以在高工作频率的低电源电压下工作，同时消耗低的电源电流。 在第二（300）和第三实施例（400）中，跟踪单元涉及一对逆变器（（301,304,302,305）或（401,404; 402,405））。 然而，逆变器的晶体管的源极耦合在一起，从而导致相对于常规电路的性能优点。

公开(公告)号：WO2010151800A2

公开(公告)日：2010-12-29

申请号：PCT/US2010/040043

申请日：2010-06-25

Applicant: QUALCOMM Incorporated ,  AHMADI, Mahmoud R. ,  SAVOJ, Jafar

Inventor： AHMADI, Mahmoud R. ,  SAVOJ, Jafar

IPC: H03L7/089

CPC classification number: H03L7/0891 ,  H03L7/1976

Abstract: A method for reducing noise in a frequency synthesizer includes selecting a design variable k , calibrating a feedback time delay (T d ), such that T d = k T VCO , where T VCO is the period of the synthesizer output signal. The method further includes estimating an instantaneous quantization error to a number of bits equal to q , defining a reference bias current of I cp /( k 2 q ), where I cp is a charge pump current signal, and applying the estimated instantaneous quantization error to a current array to produce a down modification signal (ΔI). The current array is biased by the reference bias current. The down modification signal (ΔI) is summed with the charge pump current signal I cp to modulate a down current portion of the charge pump current signal I cp .

Abstract translation: 一种用于降低频率合成器中的噪声的方法，包括选择设计变量k，校准反馈时间延迟（Td），使得Td = kTVCO，其中TVCO是合成器输出信号的周期。 该方法还包括将瞬时量化误差估计为等于q的位数，定义Icp /（k2q）的参考偏置电流，其中Icp是电荷泵电流信号，并将估计的瞬时量化误差应用于电流 阵列以产生降维修信号（ΔI）。 电流阵列被参考偏置电流偏置。 降频修正信号（ΔI）与电荷泵电流信号Icp相加，以调制电荷泵电流信号Icp的下降电流部分。

公开(公告)号：WO2007127861A2

公开(公告)日：2007-11-08

申请号：PCT/US2007/067536

申请日：2007-04-26

Applicant: RAMBUS INC. ,  THE BOARD OF TRUSTEES OF THE UNIVERSITY OF THE LELAND STANFORD JUNIOR UNIVERSITY ,  ABBASFAR, Aliazam ,  AMIRKHANY, Amir ,  SAVOJ, Jafar

Inventor： ABBASFAR, Aliazam ,  AMIRKHANY, Amir ,  SAVOJ, Jafar

IPC: G06F15/00

CPC classification number: G06F17/5036

Abstract: In a method of characterizing a circuit, a test sequence is provided. A response of the circuit to the test sequence is determined. A transfer function that corresponds to the response is determined. The transfer function is decomposed into a plurality of terms. A respective term corresponds to an nth-order term in an expansion of at least 3rd order that corresponds to the transfer function. A characteristic associated with the circuit is simulated using at least one of the terms in the plurality of terms.

Abstract translation: 在表征电路的方法中，提供测试序列。 确定电路对测试序列的响应。 确定与响应对应的传递函数。 传递函数被分解为多个项。 相应的术语对应于对应于传递函数的至少3阶的扩展中的n阶项。 使用多个术语中的至少一个术语来模拟与电路相关联的特性。

公开(公告)号：WO2012068326A1

公开(公告)日：2012-05-24

申请号：PCT/US2011/061115

申请日：2011-11-17

Applicant: QUALCOMM Incorporated ,  SOLTANIAN, Babak ,  SAVOJ, Jafar

Inventor： SOLTANIAN, Babak ,  SAVOJ, Jafar

IPC: H03L7/16 ,  H04B1/00

CPC classification number: H04B1/40 ,  H03L7/099 ,  H03L7/104 ,  H03L7/16 ,  H03L7/193 ,  H03L7/1976 ,  H04B1/0082

Abstract: A VCO of a PLL outputs a first differential signal of frequency FVCO. A first divide-by-two circuit local to the VCO divides the first differential signal and outputs a first quadrature signal of frequency FVCO/2. Two of the component signals of the first quadrature signal are routed to a second divide-by-two circuit local to a first mixer of a first device. The second divide-by-two circuit outputs a second quadrature signal of frequency FVCO/4 to the first mixer. All four signals of the first quadrature signal of frequency FVCO/2 are routed through phase mismatch correction circuitry to a second mixer of a second device. In one example, FVCO is a tunable frequency of about ten gigahertz, the first device is an IEEE802.11b/g transmitter or receiver that transmits or receives in a first band, and the second device is an IEEE802.11a transmitter or receiver that transmits or receives in a second band.

Abstract translation: PLL的VCO输出频率为FVCO的第一差分信号。 第一差分信号分频到VCO的局部区域，并输出频率为FVCO / 2的第一正交信号。 第一正交信号的分量信号中的两个被路由到第一设备的第一混频器本地的第二分频电路。 第二分频电路向第一混频器输出频率为FVCO / 4的第二正交信号。 频率为FVCO / 2的第一正交信号的所有四个信号通过相位失配校正电路被路由到第二装置的第二混频器。 在一个示例中，FVCO是约10千兆赫兹的可调频率，第一设备是在第一频带中发送或接收的IEEE802.11b / g发射机或接收机，第二设备是IEEE802.11a发射机或接收机， 或接收在第二频带。

公开(公告)号：WO2010151800A3

公开(公告)日：2011-04-07

申请号：PCT/US2010040043

申请日：2010-06-25

Applicant: QUALCOMM INC ,  AHMADI MAHMOUD R ,  SAVOJ JAFAR

Inventor： AHMADI MAHMOUD R ,  SAVOJ JAFAR

IPC: H03L7/089 ,  H03L7/197

CPC classification number: H03L7/0891 ,  H03L7/1976

Abstract: A method for reducing noise in a frequency synthesizer includes selecting a design variable k, calibrating a feedback time delay (Td), such that Td=kTVCO, where TVCO is the period of the synthesizer output signal. The method further includes estimating an instantaneous quantization error to a number of bits equal to q, defining a reference bias current of Icp/(k2 q ), where Icp is a charge pump current signal, and applying the estimated instantaneous quantization error to a current array to produce a down modification signal (?I). The current array is biased by the reference bias current. The down modification signal (?I) is summed with the charge pump current signal Icp to modulate a down current portion of the charge pump current signal Icp.

Abstract translation: 一种用于降低频率合成器中的噪声的方法，包括选择设计变量k，校准反馈时间延迟（Td），使得Td = kTVCO，其中TVCO是合成器输出信号的周期。 该方法还包括将瞬时量化误差估计为等于q的位数，定义Icp /（k2q）的参考偏置电流，其中Icp是电荷泵电流信号，并将估计的瞬时量化误差应用于电流 阵列以产生降维修信号（ΔI）。 电流阵列被参考偏置电流偏置。 降频修正信号（ΔI）与电荷泵电流信号Icp相加，以调制电荷泵电流信号Icp的下降电流部分。

公开(公告)号：WO2009099595A1

公开(公告)日：2009-08-13

申请号：PCT/US2009/000687

申请日：2009-01-30

Applicant: RAMBUS, INC. ,  LEE, Hae-Chang ,  LEIBOWITZ, Brian, S. ,  KIM, Jaeha ,  SAVOJ, Jafar

Inventor： LEE, Hae-Chang ,  LEIBOWITZ, Brian, S. ,  KIM, Jaeha ,  SAVOJ, Jafar

IPC: H04L7/033 ,  H04L7/00 ,  H04L25/03 ,  H04L25/49

CPC classification number: H04L7/0016 ,  G06Q10/06312 ,  G06Q10/103 ,  H04L7/0004 ,  H04L7/0062 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/0334 ,  H04L25/062 ,  H04L2025/0349 ,  H04L2027/004 ,  H04L2027/0067 ,  H04L2027/0069

Abstract: A receiver (102) device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Abstract translation: 接收机（102）设备利用基于边缘的时钟和数据恢复来实现增强的数据接收，例如使用闪存模数转换器架构。 在示例实施例中，设备实现第一相位调节控制回路，例如，爆炸相位检测器，其通过调整边沿时钟的相位来检测数据转换，以利用边缘采样器在最优边缘时间调整采样 的采样器。 该循环可以通过调整诸如闪存ADC的数据采样器的数据时钟的相位来进一步调整接收数据间隔中的采样以实现最佳数据接收。 该装置还可以实现具有例如波特率相位检测器的第二相位调整控制回路，波形率相位检测器检测数据间隔以便在数据采样器的最佳数据时间进一步调整采样。