Invention Application
WO2011090570A3 SEMICONDUCTOR PACKAGE WITH EMBEDDED DIE AND ITS METHODS OF FABRICATION
审中-公开
半导体封装模具包装及其制造方法
- Patent Title: SEMICONDUCTOR PACKAGE WITH EMBEDDED DIE AND ITS METHODS OF FABRICATION
- Patent Title (中): 半导体封装模具包装及其制造方法
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Application No.: PCT/US2010059237Application Date: 2010-12-07
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Publication No.: WO2011090570A3Publication Date: 2011-10-13
- Inventor: GUZEK JOHN STEPHEN , GONZALEZ JAVIER SOTO , WATTS NICHOLAS R , NALLA RAVI K
- Applicant: INTEL CORP , GUZEK JOHN STEPHEN , GONZALEZ JAVIER SOTO , WATTS NICHOLAS R , NALLA RAVI K
- Assignee: INTEL CORP,GUZEK JOHN STEPHEN,GONZALEZ JAVIER SOTO,WATTS NICHOLAS R,NALLA RAVI K
- Current Assignee: INTEL CORP,GUZEK JOHN STEPHEN,GONZALEZ JAVIER SOTO,WATTS NICHOLAS R,NALLA RAVI K
- Priority: US65533509 2009-12-29
- Main IPC: H01L23/12
- IPC: H01L23/12 ; H01L23/48
Abstract:
Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.
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