公开(公告)号：WO2011130717A2

公开(公告)日：2011-10-20

申请号：PCT/US2011/032794

申请日：2011-04-15

Applicant: INTEL CORPORATION ,  NALLA, Ravi, K. ,  AZIMI, Hamid, R. ,  GUZEK, John, S. ,  GONZALEZ, Javier Soto ,  DELANEY, Drew, W.

Inventor： NALLA, Ravi, K. ,  AZIMI, Hamid, R. ,  GUZEK, John, S. ,  GONZALEZ, Javier Soto ,  DELANEY, Drew, W.

IPC: H01L21/60 ,  H01L23/48

CPC classification number: H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将管芯附接到载体材料，其中载体材料包括由蚀刻停止层分隔的顶层和底层; 在模具附近形成电介质材料，通过在电介质材料上形成层而形成无芯衬底，然后去除顶层载体材料并从底层载体材料蚀刻停止层。

公开(公告)号：WO2011090570A3

公开(公告)日：2011-10-13

申请号：PCT/US2010059237

申请日：2010-12-07

Applicant: INTEL CORP ,  GUZEK JOHN STEPHEN ,  GONZALEZ JAVIER SOTO ,  WATTS NICHOLAS R ,  NALLA RAVI K

Inventor： GUZEK JOHN STEPHEN ,  GONZALEZ JAVIER SOTO ,  WATTS NICHOLAS R ,  NALLA RAVI K

IPC: H01L23/12 ,  H01L23/48

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/315 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/26 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2221/68345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/11831 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/26 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92132 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/40252 ,  H01L2924/40407 ,  H01L2924/40501 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10477 ,  H05K2203/0152 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

Abstract translation: 本发明的实施例描述了具有嵌入式管芯的半导体封装。 半导体封装包括含有嵌入式芯片的无芯衬底。 半导体封装提供芯片堆叠或封装堆叠功能。 此外，本发明的实施例描述了一种制造半导体封装的方法，其使组装成本最小化。

公开(公告)号：WO2011130717A3

公开(公告)日：2012-03-01

申请号：PCT/US2011032794

申请日：2011-04-15

Applicant: INTEL CORP ,  NALLA RAVI K ,  AZIMI HAMID R ,  GUZEK JOHN S ,  GONZALEZ JAVIER SOTO ,  DELANEY DREW W

Inventor： NALLA RAVI K ,  AZIMI HAMID R ,  GUZEK JOHN S ,  GONZALEZ JAVIER SOTO ,  DELANEY DREW W

IPC: H01L21/60 ,  H01L23/48

CPC classification number: H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将管芯附接到载体材料，其中载体材料包括由蚀刻停止层分隔的顶层和底层; 在模具附近形成电介质材料，通过在电介质材料上形成层而形成无芯衬底，然后去除顶层载体材料并从底层载体材料蚀刻停止层。

公开(公告)号：WO2012087474A3

公开(公告)日：2012-08-16

申请号：PCT/US2011061623

申请日：2011-11-21

Applicant: INTEL CORP ,  GONZALEZ JAVIER SOTO ,  JOMAA HOUSSAM

Inventor： GONZALEZ JAVIER SOTO ,  JOMAA HOUSSAM

IPC: H01L23/12 ,  H01L23/48

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/95 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/221 ,  H01L2224/2402 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/245 ,  H01L2224/251 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/92244 ,  H01L2224/95 ,  H01L2224/95001 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: An apparatus includes a substrate having a land side having a plurality of contact pads and a die side opposite the land side. The apparatus includes a first die and a second die wherein the first die and second die are embedded within the substrate such that the second die is located between the first die and the land side of the substrate.

Abstract translation: 一种装置包括具有接地侧的衬底，具有多个接触焊盘和与焊盘侧相对的裸片侧。 该装置包括第一管芯和第二管芯，其中第一管芯和第二管芯被嵌入衬底内，使得第二管芯位于第一管芯和衬底的焊盘侧之间。

公开(公告)号：WO2012087475A2

公开(公告)日：2012-06-28

申请号：PCT/US2011/061628

申请日：2011-11-21

Applicant: INTEL CORPORATION ,  GONZALEZ, Javier Soto ,  JOMAA, Houssam

Inventor： GONZALEZ, Javier Soto ,  JOMAA, Houssam

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L23/5384 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/06 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/02311 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/20 ,  H01L2224/2919 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81903 ,  H01L2224/8385 ,  H01L2224/92242 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.

Abstract translation: 描述了具有嵌入式堆叠硅通孔裸片的衬底。 例如，装置包括第一模具和第二模具。 第二管芯具有设置在其中的一个或多个硅通孔（TSV管芯）。 第一管芯通过一个或多个硅通孔电耦合到TSV管芯。 该设备还包括无芯衬底。 第一个裸片和TSV裸片都嵌入无芯基板中。

公开(公告)号：WO2012087475A3

公开(公告)日：2012-09-07

申请号：PCT/US2011061628

申请日：2011-11-21

Applicant: INTEL CORP ,  GONZALEZ JAVIER SOTO ,  JOMAA HOUSSAM

Inventor： GONZALEZ JAVIER SOTO ,  JOMAA HOUSSAM

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L23/5384 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/06 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/02311 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/20 ,  H01L2224/2919 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81903 ,  H01L2224/8385 ,  H01L2224/92242 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.

Abstract translation: 描述了具有嵌入式堆叠的通过硅通孔的衬底的衬底。 例如，一种装置包括第一模具和第二模具。 第二管芯具有设置在其中的一个或多个穿硅通孔（TSV管芯）。 第一管芯通过一个或多个穿硅通孔电耦合到TSV管芯。 该设备还包括无芯基板。 第一芯片和TSV芯片都嵌入在无芯基板中。

公开(公告)号：WO2012087474A2

公开(公告)日：2012-06-28

申请号：PCT/US2011/061623

申请日：2011-11-21

Applicant: INTEL CORPORATION ,  GONZALEZ, Javier Soto ,  JOMAA, Houssam

Inventor： GONZALEZ, Javier Soto ,  JOMAA, Houssam

IPC: H01L23/12 ,  H01L23/48

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/95 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/221 ,  H01L2224/2402 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/245 ,  H01L2224/251 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/92244 ,  H01L2224/95 ,  H01L2224/95001 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: An apparatus includes a substrate having a land side having a plurality of contact pads and a die side opposite the land side. The apparatus includes a first die and a second die wherein the first die and second die are embedded within the substrate such that the second die is located between the first die and the land side of the substrate.

Abstract translation: 一种装置包括衬底，衬底具有包括多个接触焊盘的焊盘侧和与焊盘侧相对的管芯侧。 该装置包括第一管芯和第二管芯，其中第一管芯和第二管芯嵌入在衬底内，使得第二管芯位于第一管芯和衬底的焊盘侧之间。

公开(公告)号：WO2011090570A2

公开(公告)日：2011-07-28

申请号：PCT/US2010/059237

申请日：2010-12-07

Applicant: INTEL CORPORATION ,  GUZEK, John, Stephen ,  GONZALEZ, Javier, Soto ,  WATTS, Nicholas, R. ,  NALLA, Ravi, K.

Inventor： GUZEK, John, Stephen ,  GONZALEZ, Javier, Soto ,  WATTS, Nicholas, R. ,  NALLA, Ravi, K.

IPC: H01L23/12 ,  H01L23/48

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/315 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/26 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2221/68345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/11831 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/26 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92132 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/40252 ,  H01L2924/40407 ,  H01L2924/40501 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10477 ,  H05K2203/0152 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

Abstract translation: 本发明的实施例描述了具有嵌入式管芯的半导体封装。 该半导体封装包括一个包含嵌入式裸片的无芯基板。 半导体封装提供管芯堆叠或封装堆叠功能。 此外，本发明的实施例描述了一种制造半导体封装的方法，其使组装成本最小化。