Provided is a system including a group of error-detecting/correcting-code self-checked/self-timed/self-corrected circuits for logic robust and performance scalable nanoelectronic design, including: (1) a combinational logic network that outputs an error-detecting/error-correcting code (EDC/ECC); and (2) an error-detecting module which gates an external clock (in a self-checked circuit), or generates an internal clock (in a self-timed circuit), and/or an error-correcting module which corrects the sequential element states (in a self-corrected circuit). Also provided is a method for implementing an error-detecting/error-correcting code (EDC/ECC) self-checked/timed/corrected circuit. The method includes (1) encoding combinational logic outputs in an error-detecting/correcting code (EDC/ECC), (2) synthesizing combinational logic, and (4) generating a gated clock in a self-checked circuit, an internal clock in a self-timed circuit, and/or corrected signals in a self-corrected circuit.