公开(公告)号：WO2023028820A1

公开(公告)日：2023-03-09

申请号：PCT/CN2021/115593

申请日：2021-08-31

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： LUO, Xianwu

IPC: G11C29/42 ,  G11C16/04

Abstract: A system includes a memory device for storing memory data. The memory device includes an array of memory cells and a plurality of word lines arranged in a plurality of rows and coupled to the array of memory cells. The system also includes a memory controller, having a processor and a memory, operatively coupled to the array of memory cells. The system further includes a host, having another processor and another memory, operatively coupled to the memory controller. The other processor of the host is configured to perform a first RAID encode operation on memory data to form first parity data. The processor of the memory controller is configured to receive the first parity data and the memory data, and perform a second RAID encode operation on the first parity data and the memory data to form second parity data.

公开(公告)号：WO2022261197A1

公开(公告)日：2022-12-15

申请号：PCT/US2022/032661

申请日：2022-06-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： BEDESCHI, Ferdinando

IPC: G11C8/10 ,  G11C7/08 ,  G11C29/42

Abstract: Apparatuses and methods for compensating for signal drop in memory. Compensating for signal drop can include applying a first signal to a terminal of a particular transistor and mirroring the first signal to a decoder replica. Compensating for signal drop can also include applying a second signal to a gate of the particular transistor, the second signal comprising a sensing signal and a signal drop on the decoder replica and sensing a state of the particular transistor.

公开(公告)号：WO2022151724A1

公开(公告)日：2022-07-21

申请号：PCT/CN2021/111492

申请日：2021-08-09

Applicant: 长鑫存储技术有限公司

Inventor： 冀康灵

IPC: G11C29/42 ,  G11C29/00

Abstract: 本申请实施例提供一种纠错系统，包括M个译码单元，被配置为对X个第一运算码以及Y个第二运算码进行译码处理；其中，译码单元包括：译码器，被配置为接收X个第一运算码并输出N个第一译码信号，每一第一译码信号与N个数据的一比特位对应；第一与门单元，被配置为接收Z个选中运算码，并进行逻辑与运算；或非门单元，被配置为接收(Y-Z)个未选运算码，并进行逻辑或非运算；N个第二与门单元，每一第二与门单元的输入端连接第一与门单元的输出端、或非门单元的输出端以及一第一译码信号，基于N个第二与门单元的输出对存储系统进行检错和/或纠错。

公开(公告)号：WO2022068263A1

公开(公告)日：2022-04-07

申请号：PCT/CN2021/099988

申请日：2021-06-15

Applicant: 长鑫存储技术有限公司

Inventor： 王佳 ,  孙圆圆

IPC: G11C29/42

Abstract: 本申请实施例提供一种存储器和存储器的测试方法，其中，存储器包括：存储模块，用于存储数据信息，存储模块包括主存储模块和校验位存储模块，主存储模块用于存储有效数据，校验位存储模块用于存储校验位数据；读写驱动模块，与存储模块连接，用于从存储模块中读取数据信息，或将数据信息写入存储模块；数据处理模块，与读写驱动模块连接，用于对读写驱动模块输出的数据信息进行检错纠错的解码操作，或用于对输入到读写驱动模块的数据信息进行检错纠错的编码操作。

公开(公告)号：WO2021252163A1

公开(公告)日：2021-12-16

申请号：PCT/US2021/033457

申请日：2021-05-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YAMAMOTO, Nobuo ,  MORGAN, Donald, Martin ,  WONG, Victor ,  KWAK, Jongtae

IPC: G11C11/22 ,  G06F11/10 ,  G11C11/221 ,  G11C11/401 ,  G11C16/10 ,  G11C16/26 ,  G11C29/20 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.

公开(公告)号：WO2021242444A1

公开(公告)日：2021-12-02

申请号：PCT/US2021/028271

申请日：2021-04-21

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： SHAH, Monish Shantilal ,  BENNETT, John Grant

IPC: G06F12/02 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F12/06 ,  G11C11/15 ,  G06F11/10 ,  G11C29/42

Abstract: Systems and methods related to a memory system with a predictable read latency from media with a long write latency are described. An example memory system includes an array of tiles configured to store data corresponding to a cache line associated with a host. The memory system further includes control logic configured to, in response to a write command from a host, initiate writing of a first cache line to a first tile in a first row of the tiles, a second cache line to a second tile in a second row of the tiles, a third cache line to a third tile in a third row of the tiles, and a fourth cache line in a fourth row of the tiles. The control logic is configured to, in response to a read command from the host, initiate reading of data stored in an entire row of tiles.

公开(公告)号：WO2021162892A1

公开(公告)日：2021-08-19

申请号：PCT/US2021/016198

申请日：2021-02-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： BOEHM, Aaron, P. ,  SCHAEFER, Scott, E.

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  G11C11/4096

Abstract: Methods, systems, and devices for internal error correction for memory devices are described. A memory device may perform a read operation at a memory array having a data partition and an error check partition and may obtain a first set of bits from the data partition and a second set of bits from the error check partition. The memory device may determine a first error detection result based on a value of a determined syndrome. The memory device may obtain a parity bit from the first set of bits and determine a second error detection result based on a comparison of the parity bit with a second function of the subset of the first set of bits. The memory device may transmit the first set of bits to a host device based at least in part on the first and second error detection results.

公开(公告)号：WO2021040965A1

公开(公告)日：2021-03-04

申请号：PCT/US2020/044656

申请日：2020-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： VECHES, Anthony, D.

IPC: G11C29/42 ,  G11C29/52 ,  G06F11/10 ,  G06F13/16 ,  G06F3/06

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled — e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.

公开(公告)号：WO2021025864A1

公开(公告)日：2021-02-11

申请号：PCT/US2020/043133

申请日：2020-07-22

Applicant: CYPRESS SEMICONDUCTOR CORPORATION

Inventor： WHATELY, Morgan ,  ZITLAW, Cliff

IPC: G06F11/00 ,  G11C7/10 ,  G11C29/42

Abstract: A method can include, in response to receiving a read request at a memory controller, sending a read command and address values on a command address bus in synchronism with a clock. In response to the read command, receiving an uninterrupted burst of read data values on at least one parallel data bus, the burst of read data values having double date rate with respect to the clock, and receiving error correction code (ECC) values for the read data values in response to the same read command, the ECC values not being included in the burst of read data values being output on non-ECC input/outputs (I/Os); wherein the non-ECC I/Os are I/Os not assigned to ECC data according to a preexisting standards organization. Corresponding systems and devices are disclosed.

公开(公告)号：WO2020185248A1

公开(公告)日：2020-09-17

申请号：PCT/US2019/043106

申请日：2019-07-23

Applicant: MICROSEMI SOC CORP.

Inventor： XUE, Fengliang ,  DHAOUI, Fethi ,  SINGARAJU, Pavan ,  NGUYEN, Victor ,  MCCOLLUM, John, L. ,  HECHT, Volker

IPC: G11C11/412 ,  G11C5/00 ,  G11C13/00 ,  G11C14/00 ,  G11C11/00 ,  G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  H01L45/00 ,  G11C29/04

Abstract: A single-event-upset (SEU) stabilized memory cell includes a latch portion including a cross-coupled latch, and at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors.