A memory system (10) including a one time programmable (OTP) memory (16) is provided. The memory system (10) further includes a write enable verification circuit (14) including an asymmetric inverter stage (30) and a symmetric inverter stage (32) coupled at a node (34). The write enable verification circuit (14) is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node (34) changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node (34) changes at a second rate higher than the first rate. The write enable verification circuit (14) is further configured to generate a verified write enable signal for enabling programming of the OTP memory (16).