公开(公告)号：WO2007047589A1

公开(公告)日：2007-04-26

申请号：PCT/US2006/040388

申请日：2006-10-13

Applicant: FREESCALE SEMICONDUCTOR INC. ,  MOOSA, Mohamed S. ,  KALPAT, Sriram S. ,  MATTHEW, Leo

Inventor： MOOSA, Mohamed S. ,  KALPAT, Sriram S. ,  MATTHEW, Leo

IPC: H03M1/12

CPC classification number: H03M1/361 ,  H01L27/0886 ,  H01L27/1211 ,  H03M1/745

Abstract: An analog to digital converter (10) including a plurality of multiple independent gate field effect transistors (MIGFET) (14, 16, 18, 20) that provide a plurality of digital output signals, is provided. Each MIGFET (14) of the plurality of MIGFETs (14, 16, 18, 20) may have first gate (60) for receiving an analog signal, a second gate (62) for being biased, and a current electrode for providing a digital output signal from among the plurality of the digital output signals. Each MIGFET of the plurality of MIGFETs may have a combination of body width, channel length that is unique among the plurality of MIGFETs to result in a threshold voltage that is unique among the plurality of MIGFETs. A digital to analog converter including a plurality of MIGFETs is also provided.

Abstract translation: 提供了包括提供多个数字输出信号的多个独立的栅极场效应晶体管（MIGFET）（14,16,18,20））的模数转换器（10）。 多个MIGFET（14,16,18,20）中的每个MIGFET（14）可以具有用于接收模拟信号的第一栅极（60），用于偏置的第二栅极（62）和用于提供数字 从多个数字输出信号中输出信号。 多个MIGFET的每个MIGFET可以具有体宽度，多个MIGFET之间唯一的沟道长度的组合，以产生多个MIGFET中唯一的阈值电压。 还提供了包括多个MIGFET的数模转换器。

公开(公告)号：WO2007047164A2

公开(公告)日：2007-04-26

申请号：PCT/US2006/039177

申请日：2006-10-04

Applicant: FREESCALE SEMICONDUCTOR INC. ,  KALPAT, Sriram S. ,  MATHEW, Leo ,  MOOSA, Mohamed S. ,  SADD, Michael A. ,  SANCHEZ, Hector

Inventor： KALPAT, Sriram S. ,  MATHEW, Leo ,  MOOSA, Mohamed S. ,  SADD, Michael A. ,  SANCHEZ, Hector

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/0995

Abstract: A voltage controlled oscillator (VCO) (40) has a plurality (42, 44, 46) of series-connected inverters. Within each inverter a first transistor (48) has a first current electrode coupled to a first power supply voltage terminal (VDD), a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of series-connected inverters, and a second control electrode for receiving a first bias signal. A second transistor (50) has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal (VSS), and a first control electrode coupled to the first control electrode of the first transistor. The second control electrode of the first transistor of each inverter receives a same or separate analog control signal (VGP, VPP OR DNP) to adjust the threshold voltage of the first transistors thereof to affect frequency and phase of the VCO's signal.

Abstract translation: 压控振荡器（VCO）（40）具有多个（42,44,46）串联逆变器。 在每个逆变器内，第一晶体管（48）具有耦合到第一电源电压端（VDD）的第一电流电极，第二电流电极，耦合到多个串联连接的另一个反相器的输出端的第一控制电极 逆变器和用于接收第一偏置信号的第二控制电极。 第二晶体管（50）具有耦合到第一晶体管的第二电流电极的第一电流电极，耦合到第二电源电压端子（VSS）的第二电流电极和耦合到第一控制电极的第一控制电极的第一控制电极 第一个晶体管。 每个逆变器的第一晶体管的第二控制电极接收相同或分开的模拟控制信号（VGP，VPP或DNP），以调整其第一晶体管的阈值电压以影响VCO信号的频率和相位。

公开(公告)号：WO2007047164A3

公开(公告)日：2007-09-27

申请号：PCT/US2006039177

申请日：2006-10-04

Applicant: FREESCALE SEMICONDUCTOR INC ,  KALPAT SRIRAM S ,  MATHEW LEO ,  MOOSA MOHAMED S ,  SADD MICHAEL A ,  SANCHEZ HECTOR

Inventor： KALPAT SRIRAM S ,  MATHEW LEO ,  MOOSA MOHAMED S ,  SADD MICHAEL A ,  SANCHEZ HECTOR

IPC: H03B1/00

CPC classification number: H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/0995

Abstract: A voltage controlled oscillator (VCO) (40) has a plurality (42, 44, 46) of series-connected inverters. Within each inverter a first transistor (48) has a first current electrode coupled to a first power supply voltage terminal (VDD), a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of series connected inverters, and a second control electrode for receiving a first bias signal. A second transistor (50) has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal (Vss), and a first control electrode coupled to the first control electrode of the first transistor. The second control electrode of the first transistor of each inverter receives a same or separate analog control signal (VGp, VPP OR DNP) to adjust the threshold voltage of the first transistors thereof to affect frequency and phase of the VCO's signal.

Abstract translation: 压控振荡器（VCO）（40）具有多个（42,44,46）串联逆变器。 在每个逆变器内，第一晶体管（48）具有耦合到第一电源电压端子（VDD）的第一电流电极，第二电流电极，耦合到多个串联连接的逆变器中的另一个反相器的输出端子的第一控制电极 以及用于接收第一偏置信号的第二控制电极。 第二晶体管（50）具有耦合到第一晶体管的第二电流电极的第一电流电极，耦合到第二电源电压端子（Vss）的第二电流电极，以及耦合到第一控制电极的第一控制电极的第一控制电极 第一个晶体管。 每个逆变器的第一晶体管的第二控制电极接收相同或分开的模拟控制信号（VGp，VPP或DNP），以调整其第一晶体管的阈值电压以影响VCO信号的频率和相位。

公开(公告)号：WO2011136948A3

公开(公告)日：2012-02-02

申请号：PCT/US2011032739

申请日：2011-04-15

Applicant: FREESCALE SEMICONDUCTOR INC ,  HOEFLER ALEXANDER B ,  MOOSA MOHAMED S

Inventor： HOEFLER ALEXANDER B ,  MOOSA MOHAMED S

IPC: G11C17/00 ,  G11C16/34

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: A memory system (10) including a one time programmable (OTP) memory (16) is provided. The memory system (10) further includes a write enable verification circuit (14) including an asymmetric inverter stage (30) and a symmetric inverter stage (32) coupled at a node (34). The write enable verification circuit (14) is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node (34) changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node (34) changes at a second rate higher than the first rate. The write enable verification circuit (14) is further configured to generate a verified write enable signal for enabling programming of the OTP memory (16).

Abstract translation: 提供了包括一次可编程（OTP）存储器（16）的存储器系统（10）。 存储器系统（10）还包括写入使能验证电路（14），其包括耦合在节点（34）处的非对称反相器级（30）和对称反相器级（32）。 写使能验证电路（14）被配置为接收写使能信号。 当写使能信号从第一电压电平变为第二电压电平时，节点（34）处的电压以第一速率变化，并且其中当写使能信号从第二电压电平变为第一电压电平时， 节点（34）处的电压以比第一速率高的第二速率改变。 写使能验证电路（14）还被配置为产生用于实现OTP存储器（16）的编程的经验证的写使能信号。

公开(公告)号：WO2011136948A2

公开(公告)日：2011-11-03

申请号：PCT/US2011/032739

申请日：2011-04-15

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  HOEFLER, Alexander B. ,  MOOSA, Mohamed S.

Inventor： HOEFLER, Alexander B. ,  MOOSA, Mohamed S.

IPC: G11C17/00 ,  G11C16/34

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: A memory system (10) including a one time programmable (OTP) memory (16) is provided. The memory system (10) further includes a write enable verification circuit (14) including an asymmetric inverter stage (30) and a symmetric inverter stage (32) coupled at a node (34). The write enable verification circuit (14) is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node (34) changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node (34) changes at a second rate higher than the first rate. The write enable verification circuit (14) is further configured to generate a verified write enable signal for enabling programming of the OTP memory (16).

Abstract translation: 提供了包括一次可编程（OTP）存储器（16）的存储器系统（10）。 存储器系统（10）还包括写入使能验证电路（14），其包括耦合在节点（34）处的非对称反相器级（30）和对称反相器级（32）。 写使能验证电路（14）被配置为接收写使能信号。 当写使能信号从第一电压电平变为第二电压电平时，节点（34）处的电压以第一速率变化，并且其中当写使能信号从第二电压电平变为第一电压电平时， 节点（34）处的电压以比第一速率高的第二速率改变。 写使能验证电路（14）还被配置为产生用于实现OTP存储器（16）的编程的经验证的写使能信号。