Invention Application
- Patent Title: SIMULTANEOUS WAFER BONDING AND INTERCONNECT JOINING
- Patent Title (中): 同时连接和互连
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Application No.: PCT/US2011/030871Application Date: 2011-04-01
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Publication No.: WO2012087364A1Publication Date: 2012-06-28
- Inventor: OGANESIAN, Vage , HABA, Belgacem , MOHAMMED, Ilyas , SAVALIA, Piyush , MITCHELL, Craig
- Applicant: TESSERA, INC. , OGANESIAN, Vage , HABA, Belgacem , MOHAMMED, Ilyas , SAVALIA, Piyush , MITCHELL, Craig
- Applicant Address: 3025 Orchard Parkway San Jose, CA 95134 US
- Assignee: TESSERA, INC.,OGANESIAN, Vage,HABA, Belgacem,MOHAMMED, Ilyas,SAVALIA, Piyush,MITCHELL, Craig
- Current Assignee: TESSERA, INC.,OGANESIAN, Vage,HABA, Belgacem,MOHAMMED, Ilyas,SAVALIA, Piyush,MITCHELL, Craig
- Current Assignee Address: 3025 Orchard Parkway San Jose, CA 95134 US
- Agency: HUMKEY, Charles, H. et al.
- Priority: US61/424,906 20101220
- Main IPC: H01L21/98
- IPC: H01L21/98 ; H01L25/065
Abstract:
Disclosed are a microelectronic assembly (300) of two elements (100, 200) and a method of forming same. A microelectronic element (100) includes a major surface (102), and a dielectric layer (120) and at least one bond pad (110) exposed at the major surface (102). The microelectronic element (100) may contain a plurality of active circuit elements. A first metal layer (130) is deposited overlying the at least one bond pad (110) and the dielectric layer (120). A second element (200) having a second metal layer (230) deposited thereon is provided, and the first metal layer (130) is joined with the second metal layer (230). The assembly (300) may be severed along dicing lanes (301) into individual units each including a chip.
Information query
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