Abstract:
A component 10 can include a substrate 20 having a front surface 22 and a rear surface 21 remote therefrom, an opening 30 extending from the rear surface towards the front surface, and a conductive via 40 extending within the opening. The substrate 20 can have a CTE less than 10 ppm/°C. The opening 30 can define an inner surface 31 between the front and rear surfaces 22, 21. The conductive via 40 can include a first metal layer 41 overlying the inner surface 31 and a second metal region 42 overlying the first metal layer and electrically coupled to the first metal layer. The second metal region 42 can have a CTE greater than a CTE of the first metal layer 41. The conductive via 40 can have an effective CTE across a diameter D of the conductive via that is less than 80% of the CTE of the second metal region 42.
Abstract:
A component 10 can include a substrate 20 having a front surface 22 and a rear surface 21 remote therefrom, an opening 30 extending from the rear surface towards the front surface, and a conductive via 40 extending within the opening. The substrate 20 can have a CTE less than 10 ppm/°C. The opening 30 can define an inner surface 31 between the front and rear surfaces 22, 21. The conductive via 40 can include a first metal layer 41 overlying the inner surface 31 and a second metal region 42 overlying the first metal layer and electrically coupled to the first metal layer. The second metal region 42 can have a CTE greater than a CTE of the first metal layer 41. The conductive via 40 can have an effective CTE across a diameter D of the conductive via that is less than 80% of the CTE of the second metal region 42.
Abstract:
A microelectronic package (10) may have a plurality of terminals (36) disposed at a face (32) thereof which are configured for connection to at least one external component, e.g., a circuit panel (70). First and second microelectronic elements (12), (14) can be affixed with packaging structure (30) therein. A first electrical connection (51A, 40A, 74A) can extend from a respective terminal (36A) of the package (10) to a corresponding contact (20A) on the first microelectronic element (12), and a second electrical connection (53A, 40B, 52A) can extend from the respective terminal (36A) to a corresponding contact (26A) on the second microelectronic element (14), the first and second connections being configured such that a respective signal carried by the first and second connections is subject to propagation delay of the same duration between the respective terminal (36A) and each of the corresponding contacts (20A, 26A) coupled thereto.
Abstract:
A component 10 can include a substrate 20 having a front surface 22 and a rear surface 21 remote therefrom, an opening 30 extending from the rear surface towards the front surface, and a conductive via 40 extending within the opening. The substrate 20 can have a CTE less than 10 ppm/°C. The opening 30 can define an inner surface 31 between the front and rear surfaces 22, 21. The conductive via 40 can include a first metal layer 41 overlying the inner surface 31 and a second metal region 42 overlying the first metal layer and electrically coupled to the first metal layer. The second metal region 42 can have a CTE greater than a CTE of the first metal layer 41. The conductive via 40 can have an effective CTE across a diameter D of the conductive via that is less than 80% of the CTE of the second metal region 42.
Abstract:
A microelectronic assembly 100 can include a substrate 102 having first and second surfaces 104, 106 and first and second openings 116, 126 extending between the first and second surfaces, the first and second openings each having a long dimension extending in respective first and second transverse directions. The microelectronic assembly 100 can also have first and second microelectronic elements 136, 153 each having bond pads 142, 159 in a central region 924, 932 of a front surface 140, 157 thereof aligned with the respective first and second openings 116, 126. The front surface 140 of the first microelectronic element 136 can confront the first surface 104, and the front surface 157 of the second microelectronic element 153 can face a rear surface 138 of the first microelectronic element and can project beyond an edge 146 of the first microelectronic element. The bond pads 142, 159 of the first and second microelectronic elements 136, 153 can be electrically connected to conductive elements 109, 111 of the substrate 102.
Abstract:
A module 10 can include a module card 40 and first and second microelectronic elements 20, 30 having front surfaces 21, 31 facing a first surface 41 of the module card. The module card 40 can also have a second surface 42 and a plurality of parallel exposed edge contacts 50 adjacent an edge 43 of at least one of the first and second surfaces 41, 42 for mating with corresponding contacts 1207 of a socket 1205 when the module 10 is inserted in the socket. Each microelectronic element 20, 30 can be electrically connected to the module card 40. The front surface 31 of the second microelectronic element 30 can partially overlie a rear surface 22 of the first microelectronic element 20 and can be attached thereto.
Abstract:
A microelectronic assembly 10 can include a substrate 30 having an aperture 39 extending between first and second surfaces 34, 32 thereof, substrate contacts 41 at the first surface, and terminals 36 at the second surface. The microelectronic assembly 10 can include a first microelectronic element 12 having a front surface 16 facing the first surface 34, a second microelectronic element 14 having a front surface 22 facing the first microelectronic element, and leads 50 electrically connecting contacts 26 of the second microelectronic element with the terminals 36. The contacts 26 of the second microelectronic element 14 can be exposed at the front surface 22 beyond an edge 29 of the first microelectronic element 12. The first microelectronic element 12 can be configured to regenerate at least some signals received by the microelectronic assembly 10 at the terminals 36 and to transmit said signals to the second microelectronic element 14.
Abstract:
A method for making a microelectronic assembly includes providing a microelectronic element 30 with first conductive elements and a dielectric element 50 with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts 40 and other of the first or second conductive elements may include a bond metal 10 disposed between some of the conductive posts 40. An underfill layer 60 may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer 60 and at least deform the bond metal 10. The microelectronic element 30 and the dielectric element 50 can be heated to join them together. The height of the posts 40 above the surface may be at least forty percent of a distance between surfaces of the microelectronic element 30 and dielectric element 50.
Abstract:
A microelectronic package (10) includes a substrate (20) having a first region (26), a second region (28), a first surface (22), and a second surface (24) remote from the first surface (22). At least one microelectronic element (60) overlies the first region (26) on the first surface (229. First electrically conductive elements (30) are exposed at one of the first surface (22) and the second surface (24) of the substrate (20) within the second (28) region with at least some of the first conductive elements (30) electrically connected to the at least one microelectronic element (60). Substantially rigid metal elements (40) overlie the first conductive elements (30) and have end surfaces (42) remote therefrom. A bond metal (41) joins the metal elements (40) with the first conductive elements (30), and a molded dielectric layer (50) overlies at least the second region (28) of the substrate (20) and has a surface (52) remote from the substrate (20). The end surfaces (42) of the metal elements (40) are at least partially exposed at the surface (52) of the molded dielectric layer (50).
Abstract:
A microelectronic assembly (100) can include first and second microelectronic elements (102, 112) each embodying active semiconductor devices adjacent a front surface (104, 114) thereof, and an interposer (120) of a material having a CTE less than 10 ppm/°C. Each microelectronic element (102, 112) can have a conductive pad (106, 116) exposed at the respective front surface (104, 114). The interposer (120) can have a second conductive element (118) extending within an opening (222) in the interposer and exposed at first and second surfaces (227, 229) of the interposer. The first and second surfaces (227, 229) can face the front surface (104, 114) of the respective first and second microelectronic elements (102, 112). Each microelectronic element (102, 112) can include a first conductive element (236, 238) extending within an opening (206, 216) extending from a rear surface (237, 239) towards the front surface (104, 114) of the respective microelectronic element. At least one of the first conductive elements (236, 238) can extend through the conductive pad (204, 214) of the respective first or second microelectronic element (102, 112).