Invention Application
WO2012134555A1 SYSTEMS, APPARATUSES, AND METHODS FOR STRIDE PATTERN GATHERING OF DATA ELEMENTS AND STRIDE PATTERN SCATTERING OF DATA ELEMENTS
审中-公开
用于数据元素的矩形图案的数据，装置和方法以及数据元素的矩形图案散射
- Patent Title: SYSTEMS, APPARATUSES, AND METHODS FOR STRIDE PATTERN GATHERING OF DATA ELEMENTS AND STRIDE PATTERN SCATTERING OF DATA ELEMENTS
- Patent Title (中): 用于数据元素的矩形图案的数据，装置和方法以及数据元素的矩形图案散射
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Application No.: PCT/US2011/063590Application Date: 2011-12-06
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Publication No.: WO2012134555A1Publication Date: 2012-10-04
- Inventor: VALENTINE, Robert, C. , HUGHES, Christopher, J. , SAN ADRIAN, Jesus, Corbal , SANS, Roger, Espasa , TOLL, Bret , GIRKAR, Milind, Baburao , FORSYTH, Andrew, Thomas , GROCHOWSKI, Edward, Thomas , HALL, Jonathan, Cannon
- Applicant: INTEL CORPORATION , VALENTINE, Robert, C. , HUGHES, Christopher, J. , SAN ADRIAN, Jesus, Corbal , SANS, Roger, Espasa , TOLL, Bret , GIRKAR, Milind, Baburao , FORSYTH, Andrew, Thomas , GROCHOWSKI, Edward, Thomas , HALL, Jonathan, Cannon
- Applicant Address: 2200 Mission College Boulevard MS: RNB-4-150 Santa Clara, CA 95052 US
- Assignee: INTEL CORPORATION,VALENTINE, Robert, C.,HUGHES, Christopher, J.,SAN ADRIAN, Jesus, Corbal,SANS, Roger, Espasa,TOLL, Bret,GIRKAR, Milind, Baburao,FORSYTH, Andrew, Thomas,GROCHOWSKI, Edward, Thomas,HALL, Jonathan, Cannon
- Current Assignee: INTEL CORPORATION,VALENTINE, Robert, C.,HUGHES, Christopher, J.,SAN ADRIAN, Jesus, Corbal,SANS, Roger, Espasa,TOLL, Bret,GIRKAR, Milind, Baburao,FORSYTH, Andrew, Thomas,GROCHOWSKI, Edward, Thomas,HALL, Jonathan, Cannon
- Current Assignee Address: 2200 Mission College Boulevard MS: RNB-4-150 Santa Clara, CA 95052 US
- Agency: MALLIE, Michael, J. et al.
- Priority: US13/078,891 20110401
- Main IPC: G06F9/30
- IPC: G06F9/30
Abstract:
Embodiments of systems, apparatuses, and methods for performing gather and scatter stride instruction in a computer processor are described. In some embodiments, the execution of a gather stride instruction causes a conditionally storage of strided data elements from memory into the destination register according to at least some of bit values of a writemask
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