公开(公告)号：WO2012134560A1

公开(公告)日：2012-10-04

申请号：PCT/US2011/064486

申请日：2011-12-12

Applicant: INTEL CORPORATION ,  SAN ADRIAN, Jesus Corbal ,  TOLL, Bret L. ,  VALENTINE, Robert C. ,  WIEDEMEIER, Jeffrey G. ,  SAMUDRALA, Sridhar ,  GIRKAR, Milind Baburao ,  FORSYTH, Andrew Thomas ,  OULD-AHMED-VALL, Elmoustapha ,  BRADFORD, Dennis R. ,  WU, Lisa K.

Inventor： SAN ADRIAN, Jesus Corbal ,  TOLL, Bret L. ,  VALENTINE, Robert C. ,  WIEDEMEIER, Jeffrey G. ,  SAMUDRALA, Sridhar ,  GIRKAR, Milind Baburao ,  FORSYTH, Andrew Thomas ,  OULD-AHMED-VALL, Elmoustapha ,  BRADFORD, Dennis R. ,  WU, Lisa K.

IPC: G06F9/30 ,  G06F9/305

CPC classification number: G06F9/30192 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043

Abstract: Embodiments of systems, apparatuses, and methods for performing a blend instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a data element-by-element selection of data elements of first and second source operands using the corresponding bit positions of a writemask as a selector between the first and second operands and storage of the selected data elements into the destination at the corresponding position in the destination.

Abstract translation: 描述了用于在计算机处理器中执行混合指令的系统，装置和方法的实施例。 在一些实施例中，混合指令的执行使用作为第一操作数和第二操作数之间的选择器的写入掩码的相应比特位置，逐个元素地选择第一和第二源操作数的数据元素，并存储所选择的 数据元素到达目的地的目标位置。

公开(公告)号：WO2012134555A1

公开(公告)日：2012-10-04

申请号：PCT/US2011/063590

申请日：2011-12-06

Applicant: INTEL CORPORATION ,  VALENTINE, Robert, C. ,  HUGHES, Christopher, J. ,  SAN ADRIAN, Jesus, Corbal ,  SANS, Roger, Espasa ,  TOLL, Bret ,  GIRKAR, Milind, Baburao ,  FORSYTH, Andrew, Thomas ,  GROCHOWSKI, Edward, Thomas ,  HALL, Jonathan, Cannon

Inventor： VALENTINE, Robert, C. ,  HUGHES, Christopher, J. ,  SAN ADRIAN, Jesus, Corbal ,  SANS, Roger, Espasa ,  TOLL, Bret ,  GIRKAR, Milind, Baburao ,  FORSYTH, Andrew, Thomas ,  GROCHOWSKI, Edward, Thomas ,  HALL, Jonathan, Cannon

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/3455 ,  G06F9/355 ,  G06F9/3555 ,  G06F9/383 ,  G06F9/3865

Abstract: Embodiments of systems, apparatuses, and methods for performing gather and scatter stride instruction in a computer processor are described. In some embodiments, the execution of a gather stride instruction causes a conditionally storage of strided data elements from memory into the destination register according to at least some of bit values of a writemask

Abstract translation: 描述了用于在计算机处理器中执行收集和散播步幅指令的系统，装置和方法的实施例。 在一些实施例中，收集步幅指令的执行导致根据写入掩码的位值的至少一些位置将条带数据元素从存储器有条件地存储到目的地寄存器中

公开(公告)号：WO2013101132A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067982

申请日：2011-12-29

Applicant: INTEL CORPORATION ,  FORSYTH, Andrew Thomas ,  BRADFORD, Dennis R.

Inventor： FORSYTH, Andrew Thomas ,  BRADFORD, Dennis R.

IPC: G06F13/14 ,  G06F9/30 ,  G06F9/305

CPC classification number: G06F9/30036 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30145 ,  G06F9/3818 ,  G06F9/3838

Abstract: An apparatus includes a decode unit to decode a permute instruction and a vector conflict instruction. A vector execution unit is coupled with the decode unit and includes a fully-connected interconnect. The fully-connected interconnect has at least four inputs to receive at least four corresponding data elements of at least one source vector. The fully-connected interconnect has at least four outputs. Each of the at least four inputs is coupled with each of the at least four outputs. The execution unit also includes a permute instruction execution logic coupled with the at least four outputs and operable to store a first vector result in response to the permute instruction. The execution unit also includes a vector conflict instruction execution logic coupled with the at least four outputs and operable to store a second vector result in a destination storage location in response to the vector conflict instruction.

Abstract translation: 一种装置包括解码单元，用于解码置换指令和向量冲突指令。 向量执行单元与解码单元耦合并且包括完全连接的互连。 完全连接的互连具有至少四个输入以接收至少一个源向量的至少四个对应的数据元素。 完全连接的互连至少有四个输出。 所述至少四个输入中的每一个与所述至少四个输出中的每一个耦合。 所述执行单元还包括与所述至少四个输出耦合的置换指令执行逻辑，并且可操作以响应于所述置换指令来存储第一向量结果。 执行单元还包括与至少四个输出耦合的向量冲突指令执行逻辑，并且可操作以响应于向量冲突指令将第二向量结果存储在目的地存储位置中。

公开(公告)号：WO2012134558A1

公开(公告)日：2012-10-04

申请号：PCT/US2011/064254

申请日：2011-12-09

Applicant: INTEL CORPORATION ,  SAN ADRIAN, Jesus, Corbal ,  SANS, Roger, Espasa ,  VALENTINE, Robert, C. ,  DURAN, Santiago, Galan ,  WIEDEMEIR, Jeffrey, G. ,  SAMUDRALA, Sridhar ,  GIRKAR, Milind, Baburao ,  FORSYTH, Andrew, Thomas ,  LEE, Victor, W.

Inventor： SAN ADRIAN, Jesus, Corbal ,  SANS, Roger, Espasa ,  VALENTINE, Robert, C. ,  DURAN, Santiago, Galan ,  WIEDEMEIR, Jeffrey, G. ,  SAMUDRALA, Sridhar ,  GIRKAR, Milind, Baburao ,  FORSYTH, Andrew, Thomas ,  LEE, Victor, W.

IPC: G06F9/30 ,  G06F9/305

CPC classification number: G06F9/30018 ,  G06F9/30043

Abstract: Embodiments of systems, apparatuses, and methods for performing an expand and/or compress instruction in a computer processor are described. In some embodiments, the execution of an expand instruction causes the selection of elements from a source that are to be sparsely stored in a destination based on values of the writemask and store each selected data element of the source as a sparse data element into a destination location, wherein the destination locations correspond to each writemask bit position that indicates that the corresponding data element of the source is to be stored.

Abstract translation: 描述了用于在计算机处理器中执行展开和/或压缩指令的系统，装置和方法的实施例。 在一些实施例中，扩展指令的执行导致根据写入掩码的值来稀疏地存储在目的地的源的元素的选择，并将源的每个选择的数据元素作为稀疏数据元素存储到目的地 位置，其中目的地位置对应于指示要存储源的相应数据元素的每个写入位位置。

公开(公告)号：WO2012134532A1

公开(公告)日：2012-10-04

申请号：PCT/US2011/054303

申请日：2011-09-30

Applicant: INTEL CORPORATION ,  VALENTINE, Robert, C. ,  SAN ADRIAN, Jesus, Corbal ,  SANS, Roger, Espasa ,  CAVIN, Robert, D. ,  TOLL, Bret, L. ,  DURAN, Santiago, Galan ,  WIEDEMEIER, Jeffrey, G. ,  SAMUDRALA, Sridhar ,  GIRKAR, Milind, Baburao ,  GROCHOWSKI, Edward, Thomas ,  HALL, Jonathan, Cannon ,  BRADFORD, Dennis, R. ,  OULD-AHMED-VALL, Elmoustapha ,  ABEL, James, C. ,  CHARNEY, Mark ,  ABRAHAM, Seth ,  SAIR, Suleyman ,  FORSYTH, Andrew, Thomas ,  YOUNT, Charles ,  WU, Lisa

Inventor： VALENTINE, Robert, C. ,  SAN ADRIAN, Jesus, Corbal ,  SANS, Roger, Espasa ,  CAVIN, Robert, D. ,  TOLL, Bret, L. ,  DURAN, Santiago, Galan ,  WIEDEMEIER, Jeffrey, G. ,  SAMUDRALA, Sridhar ,  GIRKAR, Milind, Baburao ,  GROCHOWSKI, Edward, Thomas ,  HALL, Jonathan, Cannon ,  BRADFORD, Dennis, R. ,  OULD-AHMED-VALL, Elmoustapha ,  ABEL, James, C. ,  CHARNEY, Mark ,  ABRAHAM, Seth ,  SAIR, Suleyman ,  FORSYTH, Andrew, Thomas ,  YOUNT, Charles ,  WU, Lisa

IPC: G06F9/30 ,  G06F9/305 ,  G06F9/06

CPC classification number: G06F9/30181 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract translation: 一种向量友好的指令格式及其执行。 根据本发明的一个实施例，处理器被配置为执行指令集。 指令集包括向量友好指令格式。 向量友好指令格式具有多个字段，包括基本操作字段，修改字段，增加操作字段和数据元素宽度字段，其中第一指令格式支持不同版本的基本操作和不同的扩充操作， 基本操作字段，修饰符字段，α字段，β字段和数据元素宽度字段中的不同值，并且其中只有一个不同的值可以被放置在基本操作字段，修饰符字段， 在指令流中的第一指令格式的指令的每次出现时的alpha字段，β字段和数据元素宽度字段。

公开(公告)号：WO2012134561A1

公开(公告)日：2012-10-04

申请号：PCT/US2011/064487

申请日：2011-12-12

Applicant: INTEL CORPORATION ,  SAN ADRIAN, Jesus Corbal ,  TOLL, Bret ,  VALENTINE, Robert C. ,  GIRKAR, Milind Baburao ,  FORSYTH, Andrew Thomas ,  CHRYSOS, George Z. ,  GROCHOWSKI, Edward Thomas ,  BRADFORD, Dennis ,  WU, Lisa, K. ,  OULD-AHMED-VALL, Elmoustapha

Inventor： SAN ADRIAN, Jesus Corbal ,  TOLL, Bret ,  VALENTINE, Robert C. ,  GIRKAR, Milind Baburao ,  FORSYTH, Andrew Thomas ,  CHRYSOS, George Z. ,  GROCHOWSKI, Edward Thomas ,  BRADFORD, Dennis ,  WU, Lisa, K. ,  OULD-AHMED-VALL, Elmoustapha

IPC: G06F9/30 ,  G06F9/305

CPC classification number: G06F9/324 ,  G06F9/30018 ,  G06F9/30058 ,  G06F9/30094

Abstract: Embodiments of systems, apparatuses, and methods for performing a jump instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a conditional jump to an address of a target instruction when all of bits of a writemask are zero, wherein the address of the target instruction is calculated using an instruction pointer of the instruction and the relative offset.

Abstract translation: 描述了用于在计算机处理器中执行跳转指令的系统，装置和方法的实施例。 在一些实施例中，当写入掩码的所有位都为零时，混合指令的执行导致到目标指令的地址的条件跳转，其中使用指令的指令指针和相对值计算目标指令的地址 抵消。