Invention Application
- Patent Title: STRESS-AWARE DESIGN FOR INTEGRATED CIRCUITS
- Patent Title (中): 集成电路应力设计
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Application No.: PCT/US2012/031299Application Date: 2012-03-29
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Publication No.: WO2012173683A1Publication Date: 2012-12-20
- Inventor: RAHMAN, Arifur
- Applicant: XILINX, INC. , RAHMAN, Arifur
- Applicant Address: 2100 Logic Drive San Jose, CA 95124 US
- Assignee: XILINX, INC.,RAHMAN, Arifur
- Current Assignee: XILINX, INC.,RAHMAN, Arifur
- Current Assignee Address: 2100 Logic Drive San Jose, CA 95124 US
- Agency: GEORGE, Thomas et al.
- Priority: US13/162,541 20110616
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/14 ; H01L23/48 ; H01L23/498 ; H01L23/00
Abstract:
A method of circuit design involving an integrated circuit (IC) having an interposer can include identifying an active resource implemented within the IC (200, 500) within a zone (465, 470, 535) of the interposer (205, 505) exposed to an amount of stress that exceeds a normalized amount of stress on the interposer and selectively assigning an element of the circuit design to be implemented within the IC to the active resource according to a stress-aware analysis of the circuit design as implemented within the IC. Another zone (620) is characterized by a substantially normalized stress throughout the other zone.
Information query
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