Invention Application
- Patent Title: SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A HORIZONTAL PARTIAL SUM IN RESPONSE TO A SINGLE INSTRUCTION
- Patent Title (中): 用于执行水平部分响应单一指令的系统，设备和方法
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Application No.: PCT/US2011/067196Application Date: 2011-12-23
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Publication No.: WO2013095634A1Publication Date: 2013-06-27
- Inventor: OULD-AHMED-VALL, Elmoustapha , HAGOG, Mostafa , VALENTINE, Robert , GRADSTEIN, Amit , RUBANOVICH, Simon , SPERBER, Zeev , GINZBURG, Boris , AVIV, Xiv
- Applicant: INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , HAGOG, Mostafa , VALENTINE, Robert , GRADSTEIN, Amit , RUBANOVICH, Simon , SPERBER, Zeev , GINZBURG, Boris , AVIV, Xiv
- Applicant Address: 2200 Mission College Boulevard M/S: RNB-4-150 Santa Clara, California 95052 US
- Assignee: INTEL CORPORATION,OULD-AHMED-VALL, Elmoustapha,HAGOG, Mostafa,VALENTINE, Robert,GRADSTEIN, Amit,RUBANOVICH, Simon,SPERBER, Zeev,GINZBURG, Boris,AVIV, Xiv
- Current Assignee: INTEL CORPORATION,OULD-AHMED-VALL, Elmoustapha,HAGOG, Mostafa,VALENTINE, Robert,GRADSTEIN, Amit,RUBANOVICH, Simon,SPERBER, Zeev,GINZBURG, Boris,AVIV, Xiv
- Current Assignee Address: 2200 Mission College Boulevard M/S: RNB-4-150 Santa Clara, California 95052 US
- Agency: NICHOLSON, David F. et al.
- Main IPC: G06F9/06
- IPC: G06F9/06 ; G06F9/30
Abstract:
Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal partial sum of packed data elements in response to a single vector packed horizontal sum instruction that includes a destination vector register operand, a source vector register operand, and an opcode are described.
Information query
