-
1.发明申请METHODS, APPARATUS, INSTRUCTIONS AND LOGIC TO PROVIDE VECTOR PACKED TUPLE CROSS-COMPARISON FUNCTIONALITY 审中-公开方法，装置，说明和逻辑提供向量包装的十字形跨比较功能
公开(公告)号：WO2016109170A1
公开(公告)日：2016-07-07
申请号：PCT/US2015/065514
申请日：2015-12-14
Applicant: INTEL CORPORATION , VALENTINE, Robert , HUGHES, Christopher, J. , CHARNEY, Mark, J. , SPERBER, Zeev , GRADSTEIN, Amit. , RUBANOVICH, Simon , GEBIL, Yuri , OULD-AHMED-VALL, Elmoustapha
Inventor： VALENTINE, Robert , HUGHES, Christopher, J. , CHARNEY, Mark, J. , SPERBER, Zeev , GRADSTEIN, Amit. , RUBANOVICH, Simon , GEBIL, Yuri , OULD-AHMED-VALL, Elmoustapha
CPC classification number: G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/3834
Abstract: Instructions and logic provide SIMD vector packed tuple cross-comparison functionality. Some processor embodiments include first and second registers with a variable plurality of data fields, each of the data fields to store an element of a first data type. The processor executes SIMD instructions for vector packed tuple cross-comparisons in some embodiments, which for each data field of a portion of data fields in a tuple of the first register, compares its corresponding element with every element of a corresponding portion of data fields in a tuple of the second register and sets mask bits corresponding to elements of the second register portion, in a bit-mask corresponding to unmasked elements of the corresponding first register portion, according to the corresponding comparison. In some embodiments bit-masks are shifted by corresponding elements in data fields of a third register. The comparison type is indicated by an immediate operand.
Abstract translation: 指令和逻辑提供SIMD向量填充元组交叉比较功能。 一些处理器实施例包括具有可变多个数据字段的第一和第二寄存器，每个数据字段用于存储第一数据类型的元素。 在一些实施例中，处理器执行用于向量填充元组交叉比较的SIMD指令，对于第一寄存器的元组中的数据字段的一部分的每个数据字段，将其相应元素与数据字段的相应部分的每个元素进行比较 根据对应的比较，在对应于相应的第一寄存器部分的未屏蔽元件的位掩码中，设置与第二寄存器部分的元件对应的掩码位的第二寄存器的元组。 在一些实施例中，位掩码由第三寄存器的数据字段中的相应元素移位。 比较类型由即时操作数指示。
-
2.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A HORIZONTAL PARTIAL SUM IN RESPONSE TO A SINGLE INSTRUCTION 审中-公开用于执行水平部分响应单一指令的系统，设备和方法
公开(公告)号：WO2013095634A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067196
申请日：2011-12-23
Applicant: INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , HAGOG, Mostafa , VALENTINE, Robert , GRADSTEIN, Amit , RUBANOVICH, Simon , SPERBER, Zeev , GINZBURG, Boris , AVIV, Xiv
Inventor： OULD-AHMED-VALL, Elmoustapha , HAGOG, Mostafa , VALENTINE, Robert , GRADSTEIN, Amit , RUBANOVICH, Simon , SPERBER, Zeev , GINZBURG, Boris , AVIV, Xiv
CPC classification number: G06F9/30036 , G06F9/30014 , G06F9/30101
Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal partial sum of packed data elements in response to a single vector packed horizontal sum instruction that includes a destination vector register operand, a source vector register operand, and an opcode are described.
Abstract translation: 用于在计算机处理器中执行的系统，装置和方法的实施例，响应于包括目的地向量寄存器操作数，源向量寄存器操作数和操作码的单向量压缩水平和指令，执行压缩数据元素的水平部分和 被描述。
-
3.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING CONVERSION OF A MASK REGISTER INTO A VECTOR REGISTER 审中-公开用于将掩码寄存器转换为矢量寄存器的系统，设备和方法
公开(公告)号：WO2013095609A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067086
申请日：2011-12-23
Applicant: INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret L. , CHARNEY, Mark J. , SPERBER, Zeev , GRADSTEIN, Amit
Inventor： OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret L. , CHARNEY, Mark J. , SPERBER, Zeev , GRADSTEIN, Amit
CPC classification number: G06F9/30036 , G06F9/30018 , G06F9/30032
Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor conversion of a mask register into a vector register in response to a single vector packed convert a mask register to a vector register instruction that includes a destination vector register operand, a source writemask register operand, and an opcode are described.
Abstract translation: 用于在计算机处理器中执行的系统，装置和方法，用于响应于单向量压缩将掩码寄存器转换为向量寄存器，将掩码寄存器转换为向量寄存器指令，所述向量寄存器指令包括目的地向量寄存器操作数，源写入掩码 寄存器操作数和操作码。
-
4.发明申请MULTIPLY ADD FUNCTIONAL UNIT CAPABLE OF EXECUTING SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE AND CLASS INSTRUCTIONS 审中-公开增加功能单元，可执行缩放，圆形，GETEXP，圆形，缩放，缩小，范围和类别指令
公开(公告)号：WO2012040632A2
公开(公告)日：2012-03-29
申请号：PCT/US2011/053094
申请日：2011-09-23
Applicant: INTEL CORPORATION , GRADSTEIN, Amit , ANDERSON, Cristina, S. , SPERBER, Zeev , RUBANOVICH, Simon , EITAN, Benny
Inventor： GRADSTEIN, Amit , ANDERSON, Cristina, S. , SPERBER, Zeev , RUBANOVICH, Simon , EITAN, Benny
CPC classification number: G06F7/57 , G06F5/01 , G06F5/012 , G06F7/483 , G06F7/49947 , G06F7/49957 , G06F7/5443 , G06F9/30014 , G06F9/3893
Abstract: A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction.
Abstract translation: 描述了一种包括用功能单元执行第一指令的方法。 第一条指令是一个乘加指令。 该方法还包括用功能单元执行第二指令。 第二条指令是一条圆形指令。
-
公开(公告)号：WO2013101232A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068242
申请日：2011-12-30
Applicant: INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL SAN ANDRIAN, Jesus , SAIR, Suleyman , TOLL, Bret L. , SPERBER, Zeev , GRADSTEIN, Amit , RUBENSTEIN, Asaf
Inventor： OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL SAN ANDRIAN, Jesus , SAIR, Suleyman , TOLL, Bret L. , SPERBER, Zeev , GRADSTEIN, Amit , RUBENSTEIN, Asaf
CPC classification number: G06F9/30032 , G06F9/30036
Abstract: A method of an aspect includes receiving a masked packed rotate instruction. The instruction indicates a first source packed data including a plurality of packed data elements, a packed data operation mask having a plurality of mask elements, at least one rotation amount, and a destination storage location. A result packed data is stored in the destination storage location in response to the instruction. The result packed data includes result data elements that each correspond to a different one of the mask elements in a corresponding relative position. Result data elements that are not masked out by the corresponding mask element include one of the data elements of the first source packed data in a corresponding position that has been rotated. Result data elements that are masked out by the corresponding mask element include a masked out value. Other methods, apparatus, systems, and instructions are disclosed.
Abstract translation: 一种方面的方法包括接收掩蔽的包装旋转指令。 指示指示包括多个打包数据元素的第一源打包数据，具有多个掩码元素的打包数据操作掩码，至少一个旋转量和目的地存储位置。 响应于该指令，结果打包数据被存储在目的地存储位置。 结果打包数据包括每个对应于相应相对位置中的不同掩模元素的结果数据元素。 未被相应的掩码元素掩蔽的结果数据元素包括在已旋转的对应位置中的第一源打包数据的数据元素中的一个。 由相应的掩码元素屏蔽的结果数据元素包括一个被屏蔽的值。 公开了其它方法，装置，系统和指令。
-
Patent Agency Ranking6.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING AN ABSOLUTE DIFFERENCE CALCULATION BETWEEN CORRESPONDING PACKED DATA ELEMENTS OF TWO VECTOR REGISTERS 审中-公开用于执行两个矢量寄存器的包装数据元素之间的绝对差分计算的系统，设备和方法
公开(公告)号：WO2013095597A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067067
申请日：2011-12-22
Applicant: INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , HAGOG, Mostafa , VALENTINE, Robert , GRADSTEIN, Amit , RUBANOVICH, Simon , SPERBER, Zeev
Inventor： OULD-AHMED-VALL, Elmoustapha , HAGOG, Mostafa , VALENTINE, Robert , GRADSTEIN, Amit , RUBANOVICH, Simon , SPERBER, Zeev
CPC classification number: G06F9/3001 , G06F9/30014 , G06F9/30036 , G06F17/10
Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor absolute difference calculation in response to a single vector packed absolute difference instruction that includes a first and second source vector register operand, a destination vector register operand, and an opcode are described.
Abstract translation: 描述了响应于包括第一和第二源向量寄存器操作数，目的向量寄存器操作数和操作码的单向量压缩绝对差指令在计算机处理器中执行绝对差计算的系统，装置和方法的实施例。
-
7.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A HORIZONTAL ADD OR SUBTRACT IN RESPONSE TO A SINGLE INSTRUCTION 审中-公开用于对单一指令执行水平添加或分类的系统，设备和方法
公开(公告)号：WO2013095658A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067246
申请日：2011-12-23
Applicant: INTEL CORPORATION , HAGOG, Mostafa , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , GRADSTEIN, Amit , RUBANOVICH, Simon , SPERBER, Zeev
Inventor： HAGOG, Mostafa , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , GRADSTEIN, Amit , RUBANOVICH, Simon , SPERBER, Zeev
CPC classification number: G06F9/30036 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30167 , G06F9/30185 , G06F15/8053 , G06F2207/5442
Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal add or subtract of packed data elements in response to a single vector packed horizontal add or subtract instruction that includes a destination vector register operand, a source vector register operand, and an opcode are describes.
Abstract translation: 用于在计算机处理器中执行的系统，装置和方法的实施例，其响应于包括目的地向量寄存器操作数，源向量寄存器操作数，单向量压缩水平加法或减法指令，对打包数据元素进行水平加减， 并且描述操作码。
-
公开(公告)号：WO2013095620A9
公开(公告)日：2013-06-27
申请号：PCT/US2011/067097
申请日：2011-12-23
Applicant: INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret, L. , CHARNEY, Mark, J. , SPERBER, Zeev , GRADSTEIN, Amit
Inventor： OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret, L. , CHARNEY, Mark, J. , SPERBER, Zeev , GRADSTEIN, Amit
Abstract: An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.
-
9.发明申请PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO GENERATE SEQUENCES OF INTEGERS IN NUMERICAL ORDER THAT DIFFER BY A CONSTANT STRIDE 审中-公开处理器，方法，系统和指令，用于生成恒定序列的数字序列中的整数序列
公开(公告)号：WO2013095564A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067014
申请日：2011-12-22
Applicant: INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , ABRAHAM, Seth , VALENTINE, Robert , SPERBER, Zeev , GRADSTEIN, Amit
Inventor： OULD-AHMED-VALL, Elmoustapha , ABRAHAM, Seth , VALENTINE, Robert , SPERBER, Zeev , GRADSTEIN, Amit
CPC classification number: G06F9/30181 , G06F9/30018 , G06F9/30032 , G06F9/30036
Abstract: A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four non-negative integers in numerical order with all integers in consecutive positions differing by a constant stride of at least two. In an aspect, storing the result including the sequence of the at least four integers is performed without calculating the at least four integers using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
Abstract translation: 一方面的方法包括接收指示目的地存储位置的指令。 结果存储在目的地存储位置以响应该指令。 结果包括以数字顺序的至少四个非负整数的序列，其中连续位置中的所有整数与至少两个的恒定步幅相差。 在一方面，使用前一条指令的结果，在不计算至少四个整数的情况下执行存储包括至少四个整数的序列的结果。 公开了其它方法，装置，系统和指令。
-
10.发明申请PACKED DATA REARRANGEMENT CONTROL INDEXES PRECURSORS GENERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开包装数据重新布置控制指标前提条件生成处理器，方法，系统和说明
公开(公告)号：WO2013095563A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067013
申请日：2011-12-22
Applicant: INTEL CORPORATION , ABRAHAM, Seth , VALENTINE, Robert , OULD-AHMED-VALL, Elmoustapha , SPERBER, Zeev , GRADSTEIN, Amit
Inventor： ABRAHAM, Seth , VALENTINE, Robert , OULD-AHMED-VALL, Elmoustapha , SPERBER, Zeev , GRADSTEIN, Amit
CPC classification number: G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/30036
Abstract: A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes the result including a sequence of at least four non-negative integers. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
Abstract translation: 一方面的方法包括接收指示目的地存储位置的指令。 结果存储在目的地存储位置以响应该指令。 结果包括结果，包括至少四个非负整数的序列。 在一个方面，使用前一条指令的结果不计算至少四个非负整数的值。 公开了其它方法，装置，系统和指令。
-
-
-
-
-
-
-
-
-
Search Results
26
records
(took 0.014 seconds)
