Invention Application
- Patent Title: CMOS MULTI-PINNED (MP) PIXEL
- Patent Title (中): CMOS多引脚(MP)像素
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Application No.: PCT/US2013/069969Application Date: 2013-11-14
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Publication No.: WO2014078465A1Publication Date: 2014-05-22
- Inventor: JANESICK, James Robert
- Applicant: SRI INTERNATIONAL
- Applicant Address: 333 Ravenswood Avenue Menlo Park, California 94025 US
- Assignee: SRI INTERNATIONAL
- Current Assignee: SRI INTERNATIONAL
- Current Assignee Address: 333 Ravenswood Avenue Menlo Park, California 94025 US
- Agency: AFRIDI, Ayan M.
- Priority: US61/727,537 20121116
- Main IPC: H01L31/062
- IPC: H01L31/062 ; H01L31/113
Abstract:
A CMOS multi-pinned pixel having very low dark current and very high charge transfer performance over that of conventional CMOS pixels is disclosed. The CMOS pixel includes epitaxial silicon and at least one transfer gate formed upon the epitaxial silicon. A pinned-photodiode is formed in the epitaxial silicon. A multi-pinned (MP) implant layer is implanted in the epitaxial silicon at least partially extending across the pinned-photodiode and substantially underlying the at least one transfer gate of the CMOS pixel to promote dark current passivation during an accumulation state and promote charge transfer during a transfer state.
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