公开(公告)号：WO2014078465A1

公开(公告)日：2014-05-22

申请号：PCT/US2013/069969

申请日：2013-11-14

Applicant: SRI INTERNATIONAL

Inventor： JANESICK, James Robert

IPC: H01L31/062 ,  H01L31/113

CPC classification number: H01L27/14887 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14645 ,  H01L27/14656 ,  H01L27/14689

Abstract: A CMOS multi-pinned pixel having very low dark current and very high charge transfer performance over that of conventional CMOS pixels is disclosed. The CMOS pixel includes epitaxial silicon and at least one transfer gate formed upon the epitaxial silicon. A pinned-photodiode is formed in the epitaxial silicon. A multi-pinned (MP) implant layer is implanted in the epitaxial silicon at least partially extending across the pinned-photodiode and substantially underlying the at least one transfer gate of the CMOS pixel to promote dark current passivation during an accumulation state and promote charge transfer during a transfer state.

Abstract translation: 公开了具有非常低的暗电流和非常高的电荷传输性能的CMOS多引脚像素，超过了传统的CMOS像素。 CMOS像素包括外延硅和形成在外延硅上的至少一个传输栅。 在外延硅中形成pined光电二极管。 多引脚（MP）注入层被注入到外延硅中，至少部分地延伸穿过钉扎光电二极管并且基本上位于CMOS像素的至少一个传输栅极的下方，以在积聚状态下促进暗电流钝化并促进电荷转移 在转移状态。