Invention Application
WO2014105132A1 SYSTEMS AND METHODS FOR IMPLEMENTING SOFT-DECISION REED-SOLOMON DECODING TO IMPROVE CABLE MODEM AND CABLE GATEWAY PERFORMANCE
审中-公开
实施软决策解决方案改进电缆调制解调器和电缆网关性能的系统和方法
- Patent Title: SYSTEMS AND METHODS FOR IMPLEMENTING SOFT-DECISION REED-SOLOMON DECODING TO IMPROVE CABLE MODEM AND CABLE GATEWAY PERFORMANCE
- Patent Title (中): 实施软决策解决方案改进电缆调制解调器和电缆网关性能的系统和方法
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Application No.: PCT/US2013/046306Application Date: 2013-06-18
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Publication No.: WO2014105132A1Publication Date: 2014-07-03
- Inventor: ARAMBEPOLA, Bernard , BADEM, Murat , SHUKLA, Parveen K. , GAMAGE, Sahan , HEWAVITHANA, Thushara , GOLDMAN, Naor
- Applicant: INTEL CORPORATION , ARAMBEPOLA, Bernard , BADEM, Murat , SHUKLA, Parveen K. , GAMAGE, Sahan , HEWAVITHANA, Thushara , GOLDMAN, Naor
- Applicant Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Assignee: INTEL CORPORATION,ARAMBEPOLA, Bernard,BADEM, Murat,SHUKLA, Parveen K.,GAMAGE, Sahan,HEWAVITHANA, Thushara,GOLDMAN, Naor
- Current Assignee: INTEL CORPORATION,ARAMBEPOLA, Bernard,BADEM, Murat,SHUKLA, Parveen K.,GAMAGE, Sahan,HEWAVITHANA, Thushara,GOLDMAN, Naor
- Current Assignee Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Agency: RAMIERZ, Ellis B.
- Priority: US13/728,022 20121227
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H04L27/34
Abstract:
A system and method are provided for implementing a soft Reed-Solomon (RS) decoding scheme, technique or algorithm to improve physical layer performance in cable modems and cable gateways. At 1024-QAM, a receiver is provided in which a signal to noise ratio is reduced by at least about 1 dB relaxing design considerations and specifications for other components in the system including for the tuner. A soft-RS-symbol generation scheme is provided to enable soft-input RC decoding in a forward error correction (FEC) module connected to a QAM demodulator. The RS decoding scheme is implemented without significantly complicating hardware or processing overhead. A typical receiver hardware requirement in an FEC module to implement the disclosed scheme may be comparatively modest, e.g., on an order of approximately 50K gates.
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