公开(公告)号：WO2013122613A1

公开(公告)日：2013-08-22

申请号：PCT/US2012/031038

申请日：2012-03-28

Applicant: INTEL CORPORATION ,  SHULMAN, Shaul ,  LOUKIANOV, Dmitrii ,  GOLDMAN, Naor ,  ARAMBEPOLA, Bernard

Inventor： SHULMAN, Shaul ,  LOUKIANOV, Dmitrii ,  GOLDMAN, Naor ,  ARAMBEPOLA, Bernard

IPC: H04L29/12 ,  H04L29/10 ,  H04L27/00

CPC classification number: H04L5/14 ,  H04L1/0041 ,  H04L1/0083 ,  H04L12/2801 ,  H04L27/0002 ,  H04M11/00 ,  H04N21/6118 ,  H04N21/6168

Abstract: Some demonstrative embodiments include devices, systems and methods of transferring information between elements of a communication device. For example, a device may include a front-end to receive an analog downstream input including a plurality of downstream data channels, and to provide a digital serial downstream output including at least one continuous stream of constant-size downstream frames including a plurality of constant-size downstream data frames, which include downstream sample data of the plurality of downstream data channels; a serial interface including at least one serial lane to transfer the at least on stream of the digital serial downstream output; and a processor to receive the digital serial downstream over the serial interface, and to process the downstream data frames.

Abstract translation: 一些演示实施例包括在通信设备的元件之间传送信息的设备，系统和方法。 例如，设备可以包括前端以接收包括多个下游数据信道的模拟下游输入，并且提供数字串行下游输出，其包括至少一个恒定尺寸的下游帧的连续流，包括多个常数 确定下游数据帧，其包括所述多个下游数据信道的下游采样数据; 串行接口，包括至少一个串行通道，用于传输数字串行下游输出的至少上游; 以及处理器，通过串行接口接收数字串行下游，并处理下游数据帧。

公开(公告)号：WO2007112253A3

公开(公告)日：2008-05-15

申请号：PCT/US2007064603

申请日：2007-03-22

Applicant: TEXAS INSTRUMENTS INC ,  GOLDMAN NAOR ,  SOMMER NAFTALI

Inventor： GOLDMAN NAOR ,  SOMMER NAFTALI

IPC: H03M3/00 ,  G06G7/38

CPC classification number: H04B14/06 ,  H04L1/0057 ,  H04L25/067 ,  H04L27/3845

Abstract: Apparatus and methods are provided for differential decoding in a communication system, such as a cable system, that enable use of Chase algorithm for Reed Solomon (RS) codes (i.e., non-binary codes). A differential decoder (170) has a memory for storing a current decoder input and a previous decoder input. Each decoder input comprises a first candidate (Input Constellation Candidate #1), a second candidate (Input Constellation Candidate #2) and a reliability score (Score). A first branch comprises a first differential decoder (192) and corresponds to the first candidate. A second branch comprises a second differential decoder (196) and corresponds to the second candidate. A processing circuit (190) is operative to determine whether a previous decoder input is a boundary point, and if not, a current first candidate is applied to the first differential decoder (192) and a current second candidate is applied to the second differential decoder (196). If a previous decoder input is a boundary point and a current input score is greater than a previous input score, a first current candidate is applied to the first differential decoder and the second differential decoder and a second differential decoder memory is set to the contents of a first differential decoder memory. If a previous decoder input is a boundary point and a current input score is not greater then a previous input score, current first and second candidates are applied to the first and second differential decoders, respectively.

Abstract translation: 提供了用于在诸如电缆系统的通信系统中的差分解码的装置和方法，其能够使用Chase算法用于里德所罗门（RS）码（即非二进制码）。 差分解码器（170）具有用于存储当前解码器输入和先前解码器输入的存储器。 每个解码器输入包括第一候选（输入星座候选者＃1），第二候选（输入星座候选者＃2）和可靠性分数（评分）。 第一分支包括第一差分解码器（192）并对应于第一候选。 第二分支包括第二差分解码器（196）并且对应于第二候选。 处理电路（190）可操作以确定先前的解码器输入是否是边界点，如果不是，则将当前第一候选应用于第一差分解码器（192），并将当前第二候选应用于第二差分解码器 （196）。 如果先前的解码器输入是边界点并且当前输入得分大于先前输入得分，则将第一当前候选应用于第一差分解码器，并且将第二差分解码器和第二差分解码器存储器设置为 第一差分解码器存储器。 如果先前的解码器输入是边界点，并且当前输入得分不大于先前的输入分数，则当前的第一和第二候选分别被施加到第一和第二差分解码器。

公开(公告)号：WO2007112253A2

公开(公告)日：2007-10-04

申请号：PCT/US2007/064603

申请日：2007-03-22

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  GOLDMAN, Naor ,  SOMMER, Naftali

Inventor： GOLDMAN, Naor ,  SOMMER, Naftali

IPC: H04B14/06 ,  H04L5/12

CPC classification number: H04B14/06 ,  H04L1/0057 ,  H04L25/067 ,  H04L27/3845

Abstract: Apparatus and methods are provided for differential decoding in a communication system, such as a cable system, that enable use of Chase algorithm for Reed Solomon (RS) codes (i.e., non-binary codes). A differential decoder (170) has a memory for storing a current decoder input and a previous decoder input. Each decoder input comprises a first candidate (Input Constellation Candidate #1), a second candidate (Input Constellation Candidate #2) and a reliability score (Score). A first branch comprises a first differential decoder (192) and corresponds to the first candidate. A second branch comprises a second differential decoder (196) and corresponds to the second candidate. A processing circuit (190) is operative to determine whether a previous decoder input is a boundary point, and if not, a current first candidate is applied to the first differential decoder (192) and a current second candidate is applied to the second differential decoder (196). If a previous decoder input is a boundary point and a current input score is greater than a previous input score, a first current candidate is applied to the first differential decoder and the second differential decoder and a second differential decoder memory is set to the contents of a first differential decoder memory. If a previous decoder input is a boundary point and a current input score is not greater then a previous input score, current first and second candidates are applied to the first and second differential decoders, respectively.

Abstract translation: 提供了用于在诸如电缆系统的通信系统中的差分解码的装置和方法，其能够使用Chase算法用于里德所罗门（RS）码（即非二进制码）。 差分解码器（170）具有用于存储当前解码器输入和先前解码器输入的存储器。 每个解码器输入包括第一候选（输入星座候选者＃1），第二候选（输入星座候选者＃2）和可靠性分数（评分）。 第一分支包括第一差分解码器（192）并对应于第一候选。 第二分支包括第二差分解码器（196）并且对应于第二候选。 处理电路（190）可操作以确定先前的解码器输入是否是边界点，如果不是，则将当前第一候选应用于第一差分解码器（192），并将当前第二候选应用于第二差分解码器 （196）。 如果先前的解码器输入是边界点并且当前输入得分大于先前的输入得分，则将第一当前候选应用于第一差分解码器，并且将第二差分解码器和第二差分解码器存储器设置为 第一差分解码器存储器。 如果先前的解码器输入是边界点，并且当前输入得分不大于先前的输入分数，则当前的第一和第二候选分别被施加到第一和第二差分解码器。

公开(公告)号：WO2014105132A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/046306

申请日：2013-06-18

Applicant: INTEL CORPORATION ,  ARAMBEPOLA, Bernard ,  BADEM, Murat ,  SHUKLA, Parveen K. ,  GAMAGE, Sahan ,  HEWAVITHANA, Thushara ,  GOLDMAN, Naor

Inventor： ARAMBEPOLA, Bernard ,  BADEM, Murat ,  SHUKLA, Parveen K. ,  GAMAGE, Sahan ,  HEWAVITHANA, Thushara ,  GOLDMAN, Naor

IPC: H03M13/00 ,  H04L27/34

CPC classification number: H04L27/06 ,  H03M13/1515 ,  H03M13/451 ,  H03M13/453 ,  H04L1/0045 ,  H04L1/0047 ,  H04L1/0057 ,  H04L27/38

Abstract: A system and method are provided for implementing a soft Reed-Solomon (RS) decoding scheme, technique or algorithm to improve physical layer performance in cable modems and cable gateways. At 1024-QAM, a receiver is provided in which a signal to noise ratio is reduced by at least about 1 dB relaxing design considerations and specifications for other components in the system including for the tuner. A soft-RS-symbol generation scheme is provided to enable soft-input RC decoding in a forward error correction (FEC) module connected to a QAM demodulator. The RS decoding scheme is implemented without significantly complicating hardware or processing overhead. A typical receiver hardware requirement in an FEC module to implement the disclosed scheme may be comparatively modest, e.g., on an order of approximately 50K gates.

Abstract translation: 提供了一种用于实现软的里德 - 所罗门（RS）解码方案，技术或算法以改善电缆调制解调器和电缆网关中的物理层性能的系统和方法。 在1024-QAM中，提供了一种接收机，其中信噪比降低了包括用于调谐器的系统中其他部件的至少约1dB的松弛设计考虑和规格。 提供软RS符号生成方案以在连接到QAM解调器的前向纠错（FEC）模块中实现软输入RC解码。 实现RS解码方案，而不会使硬件或处理开销显着复杂化。 用于实现所公开的方案的FEC模块中的典型接收机硬件要求可以是相对适中的，例如大约50K门的量级。

公开(公告)号：WO2014051798A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/048093

申请日：2013-06-27

Applicant: INTEL CORPORATION ,  SHALEM, Elihay ,  TAL, Noam ,  GOLDMAN, Naor ,  LEVY, Efrat

Inventor： SHALEM, Elihay ,  TAL, Noam ,  GOLDMAN, Naor ,  LEVY, Efrat

IPC: G06F9/38

CPC classification number: G06F13/36 ,  G06F9/462

Abstract: Some demonstrative embodiments include devices, systems and methods of multi-channel processing. For example, a multi-channel data processor may process data of a plurality of channels, the multi-channel data processor is to switch from processing a first channel to processing a second channel of the plurality of channels by performing a context switch during a single clock cycle, the context switch including storing first state context corresponding to a processing state of the first channel and loading previously stored second state context corresponding to a processing state of the second channel.

Abstract translation: 一些演示实施例包括多信道处理的设备，系统和方法。 例如，多通道数据处理器可以处理多个通道的数据，多通道数据处理器将通过在单个通道期间执行上下文切换来从处理第一通道切换到处理多个通道中的第二通道 时钟周期，所述上下文切换包括存储对应于所述第一信道的处理状态的第一状态上下文，以及加载与所述第二信道的处理状态相对应的先前存储的第二状态上下文。