Invention Application
WO2014105166A1 IMPROVED REFRESH RATE PERFORMANCE BASED ON IN-SYSTEM WEAK BIT DETECTION
审中-公开
基于系统内弱点检测的改进刷新性能
- Patent Title: IMPROVED REFRESH RATE PERFORMANCE BASED ON IN-SYSTEM WEAK BIT DETECTION
- Patent Title (中): 基于系统内弱点检测的改进刷新性能
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Application No.: PCT/US2013/047421Application Date: 2013-06-24
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Publication No.: WO2014105166A1Publication Date: 2014-07-03
- Inventor: SCHOENBORN, Theodore Z. , MOZAK, Christopher P.
- Applicant: INTEL CORPORATION
- Applicant Address: 2200 Mission College Boulevard M/S: RNB-4-150 Santa Clara, California 95054 US
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: 2200 Mission College Boulevard M/S: RNB-4-150 Santa Clara, California 95054 US
- Agency: MALLIE, Michael J. et al.
- Priority: US13/730,413 20121228
- Main IPC: G11C11/406
- IPC: G11C11/406 ; G11C11/402
Abstract:
A memory subsystem can test a memory device in situ, testing the performance of the device in the system it is built into during production. Thus, the refresh rate can be adjusted specific to the memory device(s) of a specific system, rather than defaulting to a refresh frequency specified by a standard for the memory device(s). A test component embedded within the host memory subsystem can perform a test and identify specific bits or lines of memory that produce errors when a lower frequency refresh rate is used. The system maps out the identified bits or lines to prevent the bits/lines from being used in runtime of the system. The memory subsystem can then set its refresh rate to an adjusted refresh rate at which a threshold number of errors can be removed by mapping out the bits/lines.
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