公开(公告)号：WO2011081843A2

公开(公告)日：2011-07-07

申请号：PCT/US2010/059823

申请日：2010-12-10

Applicant: INTEL CORPORATION ,  SPRY, Bryan L. ,  SCHOENBORN, Theodore Z. ,  ABRAHAM, Philip ,  MOZAK, Christopher P. ,  ELLIS, David G. ,  NEJEDLO, Jay J. ,  QUERBACH, Bruce ,  GREENFIELD, Zvika ,  GHATTAS, Rony ,  THOLIYIL, Jayasekhar ,  LUCAS, Charles D. ,  YUNKER, Christopher E.

Inventor： SPRY, Bryan L. ,  SCHOENBORN, Theodore Z. ,  ABRAHAM, Philip ,  MOZAK, Christopher P. ,  ELLIS, David G. ,  NEJEDLO, Jay J. ,  QUERBACH, Bruce ,  GREENFIELD, Zvika ,  GHATTAS, Rony ,  THOLIYIL, Jayasekhar ,  LUCAS, Charles D. ,  YUNKER, Christopher E.

IPC: G11C29/10

CPC classification number: G11C29/08 ,  G11C29/10 ,  G11C29/44

Abstract: REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.

Abstract translation: 引入了用于存储器链接的REUT（鲁棒电气统一测试），可以加速测试，开发和调试。 此外，它还提供了具有足够性能的训练钩子，以供BIOS使用，以训练过去实施中不可能的参数和条件。 还公开了地址图案生成电路。

公开(公告)号：WO2015094198A1

公开(公告)日：2015-06-25

申请号：PCT/US2013/075875

申请日：2013-12-17

Applicant: INTEL CORPORATION

Inventor： LAU, Ker Yon ,  MOZAK, Christopher P.

IPC: H03K19/003

CPC classification number: H03K19/003 ,  H01L27/0248

Abstract: Described is an apparatus which comprises: a p-type pull-up driver coupled to a pad; an n-type device operable as a first diode, the n-type device for coupling in parallel to the p-type pull-up driver; an n-type pull-down driver coupled to the pad; and a p-type device operable as a second diode, the p-type device for coupling in parallel to the n-type pull-down driver.

Abstract translation: 描述了一种装置，其包括：耦合到焊盘的p型上拉驱动器; 可操作为第一二极管的n型器件，用于与p型上拉驱动器并联耦合的n型器件; 耦合到所述垫的n型下拉驱动器; 以及可操作为第二二极管的p型器件，用于与n型下拉驱动器并联耦合的p型器件。

公开(公告)号：WO2014077902A1

公开(公告)日：2014-05-22

申请号：PCT/US2013/045025

申请日：2013-06-10

Applicant: INTEL CORPORATION ,  MOZAK, Christopher P. ,  NAVARATNAM, Navindra ,  ELASSAL, Mahmoud ,  MOZAK, Christopher P.

Inventor： MOZAK, Christopher P. ,  NAVARATNAM, Navindra ,  ELASSAL, Mahmoud ,  MOZAK, Christopher P.

IPC: G05F1/10 ,  G05F1/565

CPC classification number: G05F1/10 ,  G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/105 ,  H02M3/07 ,  H02M2003/1566

Abstract: Circuitry to provide a supply voltage. A voltage regulator is coupled to receive a target reference signal. The voltage regulator generates a supply voltage (Vtt) and is coupled to receive the supply voltage as an input signal. An upper limit comparator receives an upper limit voltage signal that is higher than the target reference voltage signal and the supply voltage to generate a "too high" signal when the supply voltage exceeds an upper threshold. A lower limit comparator receives a lower limit voltage signal that is lower than the target reference voltage signal and the supply voltage to generate a "too low" signal when the supply voltage is below a lower threshold. A pull up current source is coupled to pull the supply voltage up in response to the too low signal. A pull down current source is coupled to pull the supply voltage down in response to the too high signal.

Abstract translation: 电路提供电源电压。 电压调节器被耦合以接收目标参考信号。 电压调节器产生电源电压（Vtt）并被耦合以接收电源电压作为输入信号。 当电源电压超过上限阈值时，上限比较器接收高于目标参考电压信号和电源电压的上限电压信号，以产生“过高”信号。 下限比较器接收低于目标参考电压信号的下限电压信号和电源电压，以在电源电压低于下阈值时产生“太低”信号。 耦合上拉电流源以响应于太低的信号将电源电压拉高。 耦合下拉电流源以响应于太高的信号而将电源电压降低。

公开(公告)号：WO2016105783A1

公开(公告)日：2016-06-30

申请号：PCT/US2015/062220

申请日：2015-11-23

Applicant: INTEL CORPORATION

Inventor： TEOH, Ee Loon ,  OOI, Eng Hun ,  MOZAK, Christopher P. ,  MCFARLANE, Brian R.

IPC: H03M13/00

CPC classification number: G06F13/4282 ,  G06F13/1668 ,  G06F13/28 ,  G06F21/79 ,  Y02D10/14 ,  Y02D10/151

Abstract: An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal.

Abstract translation: I / O接口支持加扰，其中加扰可以包括扰码的非线性加扰或扰码的动态总线反转，或扰码的选定位的选择性切换，或这些的组合。 发送设备包括加扰器，并且接收设备包括解扰器。 加扰器和解扰器都产生通过应用上述一种或多种技术修改的线性反馈扰码。 经修改的扰码可能导致少于一半的加扰输出比特相对于先前的加扰输出被切换。 扰频器将修改的扰码应用于要发送的信号。 解扰器将修改的扰码应用于接收信号。

公开(公告)号：WO2015148070A1

公开(公告)日：2015-10-01

申请号：PCT/US2015/018491

申请日：2015-03-03

Applicant: INTEL CORPORATION

Inventor： KOSTINSKY, Alexey ,  LEVY, Tomer ,  CHESES, Paul S. ,  NAIGER, Danny ,  SCHOENBORN, Theodore Z. ,  MOZAK, Christopher P. ,  ABOULENEIN, Nagi ,  SHEHADI, James M.

IPC: G06F11/16 ,  G06F11/07

CPC classification number: H04B3/487 ,  G01R31/28 ,  G01R31/31855 ,  G06F11/00

Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.

Abstract translation: 在一个示例中，控制器包括至少部分地包括硬件逻辑的逻辑，其被配置为通过在第一组伪随机模式上产生第一组伪随机模式来实现在包括受害者通道和第一侵入者通道的通信互连上的干扰测试的第一次迭代 受害者车道和侵略者车道，并通过在第一侵略者车道上推进种子来实施干扰测试的第二次迭代。 可以描述其他示例。

公开(公告)号：WO2014004029A1

公开(公告)日：2014-01-03

申请号：PCT/US2013/044577

申请日：2013-06-06

Applicant: INTEL CORPORATION

Inventor： COX, Christopher E. ,  MOZAK, Christopher P. ,  LOOP, Revecca Z.

IPC: G06F13/14

CPC classification number: G06F12/063 ,  G06F12/0607

Abstract: A mechanism is described for facilitating dynamic multi-mode memory packages in memory systems according to one embodiment of the invention. A method of embodiments of the invention includes maintaining a plurality of memory modes on a single memory package at a motherboard of a computing system. The plurality of memory modes is associated with a plurality of physical organizations of memory devices. The method may further include receiving a request to switch from a first memory mode to a second memory mode of the plurality of memory mode, and dynamically switching from the first memory mode to the second memory mode, in response to the request.

Abstract translation: 描述了根据本发明的一个实施例的用于促进存储器系统中的动态多模式存储器包的机制。 本发明的实施例的方法包括在计算系统的主板上的单个存储器包上维护多个存储器模式。 多个存储器模式与存储器设备的多个物理组织相关联。 该方法还可以包括接收从多个存储器模式的第一存储器模式切换到第二存储器模式的请求，以及响应于该请求动态地从第一存储器模式切换到第二存储器模式。

公开(公告)号：WO2018081746A1

公开(公告)日：2018-05-03

申请号：PCT/US2017/059102

申请日：2017-10-30

Applicant: INTEL CORPORATION

Inventor： COX, Christopher E. ,  BAINS, Kuljit ,  MOZAK, Christopher P. ,  MCCALL, James A. ,  VASANTH, Akshith ,  NALE, Bill

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C7/10

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

Abstract translation: 存储器子系统利用片选（CS）信号线触发存储器件从低功率模式进入和退出。 对于命令总线没有时钟使能（CKE）信号线的系统，系统可以用CS而不是CKE触发低功耗模式。 低功耗模式可以包括掉电状态。 低功耗模式可以包括自刷新状态。 存储设备包括到命令总线的接口，并且在命令总线上接收与命令编码组合的CS信号以触发低功率模式状态改变。 存储设备可以配置为在低功率模式下监测CS信号和选择的其他命令信号。 即使没有专用的ODT信号线，系统也可以在存储设备处于低功率模式时发送ODT触发。

公开(公告)号：WO2016094052A1

公开(公告)日：2016-06-16

申请号：PCT/US2015/061653

申请日：2015-11-19

Applicant: INTEL CORPORATION

Inventor： MCCALL, James A. ,  MOZAK, Christopher P.

IPC: G06F13/10 ,  G06F1/32 ,  G06F13/16

CPC classification number: G11C7/1057 ,  H03K19/018585

Abstract: A memory device interface with a programmable driver. The memory device is associated with a memory controller, with one or more input/output (I/O) signal lines coupled between the memory device and the memory controller. The memory device includes an I/O signal line interface including a driver for each I/O signal line. The driver is a programmable driver to dynamically adjust an output voltage swing for transmission via the I/O signal line interface.

Abstract translation: 具有可编程驱动器的存储器设备接口。 存储器设备与存储器控制器相关联，其中一个或多个输入/输出（I / O）信号线耦合在存储器件和存储器控制器之间。 存储器件包括一个I / O信号线接口，它包括用于每个I / O信号线的驱动器。 驱动器是一个可编程驱动器，用于动态调整输出电压摆幅，以通过I / O信号线接口进行传输。

公开(公告)号：WO2014004748A1

公开(公告)日：2014-01-03

申请号：PCT/US2013/048016

申请日：2013-06-26

Applicant: INTEL CORPORATION ,  BAINS, Kuljit ,  HALBERT, John B. ,  MOZAK, Christopher P. ,  SCHOENBORN, Theodore Z. ,  GREENFIELD, Zvika

Inventor： BAINS, Kuljit ,  HALBERT, John B. ,  MOZAK, Christopher P. ,  SCHOENBORN, Theodore Z. ,  GREENFIELD, Zvika

IPC: G11C11/401 ,  G11C11/406

CPC classification number: G11C11/4091 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/7211 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as "hammered" or a "row hammer event"), physically adjacent row (a "victim" row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract translation: 内存控制器发出目标刷新命令。 存储器件的特定行可以是重复访问的目标。 当行在时间阈值（也称为“锤击”或“行锤事件”）中被重复访问时，物理上相邻的行（“受害者”行）可能经历数据损坏。 存储器控制器接收行敲击事件的指示，识别与行锤事件相关联的行，并且将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。

公开(公告)号：WO2018009299A1

公开(公告)日：2018-01-11

申请号：PCT/US2017/036390

申请日：2017-06-07

Applicant: INTEL CORPORATION

Inventor： MOZAK, Christopher P. ,  ZIA, Victor ,  THOMPSON, Gabriel J.

IPC: G11C7/10 ,  G11C7/24

CPC classification number: H01L27/0281 ,  H01L27/0255 ,  H02H9/046

Abstract: Some embodiments include apparatus and methods using a first transistor coupled between a node and a supply node, a second transistor coupled between the node and a ground node, an electrostatic discharge (ESD) protection unit including a diode coupled between the node and an additional node, and a transistor coupled between the additional node and the supply node.

Abstract translation: 一些实施例包括使用耦合在节点和电源节点之间的第一晶体管，耦合在节点和地节点之间的第二晶体管，包括二极管的静电放电（ESD）保护单元的装置和方法， 耦合在节点和附加节点之间，以及耦合在附加节点和电源节点之间的晶体管。