Invention Application
- Patent Title: REDUCING SOLDER PAD TOPOLOGY DIFFERENCES BY PLANARIZATION
- Patent Title (中): 通过平面化降低焊膏平台拓扑差异
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Application No.: PCT/IB2014/061968Application Date: 2014-06-05
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Publication No.: WO2014207590A2Publication Date: 2014-12-31
- Inventor: LEI, Jipu , SCHIAFFINO, Stefano , NICKEL, Alexander H. , NG, Mooi Guan , AKRAM, Salman
- Applicant: KONINKLIJKE PHILIPS N.V.
- Applicant Address: High Tech Campus 5 NL-5656 AE Eindhoven NL
- Assignee: KONINKLIJKE PHILIPS N.V.
- Current Assignee: KONINKLIJKE PHILIPS N.V.
- Current Assignee Address: High Tech Campus 5 NL-5656 AE Eindhoven NL
- Agency: VAN EEUWIJK, Alexander et al.
- Priority: US61/838,457 20130624
- Main IPC: H01L21/60
- IPC: H01L21/60
Abstract:
A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.
Information query
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