Invention Application
- Patent Title: Electronic Assembly for Prognostics of Solder Joint
- Patent Title (中): 焊接接头电子组装
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Application No.: PCT/JP2013/004081Application Date: 2013-07-01
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Publication No.: WO2015001583A1Publication Date: 2015-01-08
- Inventor: DIGUNA, Lina Jaya , OKAMOTO, Masahide , TAMAKI, Kenji
- Applicant: HITACHI, LTD.
- Applicant Address: 6-6, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1008280 JP
- Assignee: HITACHI, LTD.
- Current Assignee: HITACHI, LTD.
- Current Assignee Address: 6-6, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1008280 JP
- Agency: TSUTSUI, Yamato
- Main IPC: G01R31/28
- IPC: G01R31/28 ; H01L21/52
Abstract:
The problem to be solved by the present invention is to provide a substrate for providing early warning of degradation in a semiconductor device. The problem is solved by providing a substrate comprising an actual device comprising a semiconductor component and a solder joint, and a dummy device closely placed to the actual device on the substrate and connected electrically in parallel circuit to the actual device, comprising a dummy semiconductor component and a solder joint comprising an outer solder joint part and an inner solder joint part, wherein the outer solder joint part has same characteristic to the solder joint of the actual device and the inner solder joint part accelerates the crack growth faster than the outer solder joint, and percentage area of outer solder joint part is smaller than the predetermined failure criterion of delamination percentage in actual device corresponding to the threshold value of electrical change.
Information query