A method for measuring parameters of an analog signal to determine times at which the analog signal (S) crosses predetermined voltage thresholds (V A , V B , V C , V D ), the method comprising the steps of: splitting the analog signal (S) into a number of interim signals (S A , S B , S C , S D ), the number of the interim signals corresponding to the number of the preset voltage thresholds (V A , V B , V C , V D ); providing an FPGA system (10) comprising differential buffers (11 A, 11 B, 11 C, 11 D) with outputs connected to a number of sequences (20A, 20B, 20C, 20D) of delay elements (21, 22, 23), the number of sequences of delay elements corresponding to the number of the preset voltage thresholds (V A , V B , V C , V D ); inputting, to an input of each differential buffer (11 A, 11 B, 11 C, 11 D), one interim signal (S A , S B , S C , S D ) and a reference voltage corresponding to a particular preset voltage threshold (V A , V B , V C , V D ); reading, by means of vector generators (31 A, 31 B, 31 C, 31 D), assigned separately to each of the sequences (20A, 20B, 20C, 20D) and connected to a common clock signal (CLK), current values of output signals of each of the delay elements (21, 22, 23) in the particular sequence (20A, 20B, 20C, 20D) at the same moment for all vector generators and providing these values as sequence output vectors (W A , W B , W C , W D ); and determining times at which the analog signal (S) crosses the predetermined voltage thresholds (V A , V B , V C , V D ) on the basis of the values of the sequence output vectors (W A , W B , W C , W D ) and the delays introduced by the delay elements (21, 22, 23).