公开(公告)号：WO2015028600A1

公开(公告)日：2015-03-05

申请号：PCT/EP2014/068367

申请日：2014-08-29

Applicant: UNIWERSYTET JAGIELLONSKI

Inventor： PALKA, Marek ,  MOSKAL, Pawel

IPC: G04F10/00

CPC classification number: G01R19/175 ,  G01T1/2985 ,  G04F10/005 ,  G06F1/00 ,  G06F2101/00 ,  H01L21/00

Abstract: A method for measuring parameters of an analog signal to determine times at which the analog signal (S) crosses predetermined voltage thresholds (V A , V B , V C , V D ), the method comprising the steps of: splitting the analog signal (S) into a number of interim signals (S A , S B , S C , S D ), the number of the interim signals corresponding to the number of the preset voltage thresholds (V A , V B , V C , V D ); providing an FPGA system (10) comprising differential buffers (11 A, 11 B, 11 C, 11 D) with outputs connected to a number of sequences (20A, 20B, 20C, 20D) of delay elements (21, 22, 23), the number of sequences of delay elements corresponding to the number of the preset voltage thresholds (V A , V B , V C , V D ); inputting, to an input of each differential buffer (11 A, 11 B, 11 C, 11 D), one interim signal (S A , S B , S C , S D ) and a reference voltage corresponding to a particular preset voltage threshold (V A , V B , V C , V D ); reading, by means of vector generators (31 A, 31 B, 31 C, 31 D), assigned separately to each of the sequences (20A, 20B, 20C, 20D) and connected to a common clock signal (CLK), current values of output signals of each of the delay elements (21, 22, 23) in the particular sequence (20A, 20B, 20C, 20D) at the same moment for all vector generators and providing these values as sequence output vectors (W A , W B , W C , W D ); and determining times at which the analog signal (S) crosses the predetermined voltage thresholds (V A , V B , V C , V D ) on the basis of the values of the sequence output vectors (W A , W B , W C , W D ) and the delays introduced by the delay elements (21, 22, 23).

Abstract translation: 一种用于测量模拟信号的参数以确定模拟信号（S）跨过预定电压阈值（VA，VB，VC，VD）的时间的方法，所述方法包括以下步骤：将模拟信号（S）分割成 临时信号的数量（SA，SB，SC，SD），与预置电压阈值（VA，VB，VC，VD）的数量对应的中间信号的数量; 提供具有连接到多个延迟元件（21,22,23）的序列（20A，20B，20C，20D）的输出的差分缓冲器（11A，11B，11C，11D）的FPGA系统（10） ，对应于预设电压阈值（VA，VB，VC，VD）的数量的延迟元件的序列数; 将每个差分缓冲器（11A，11B，11C，11D）的输入，一个中间信号（SA，SB，SC，SD）和对应于特定预设电压阈值的参考电压（VA，VB ，VC，VD）; 通过分别分配给每个序列（20A，20B，20C，20D）并连接到公共时钟信号（CLK）的矢量发生器（31A，31B，31C，31D）读取电流值 （20A，20B，20C，20D）中的每个延迟元件（21,22,23）的输出信号，并且将这些值作为序列输出向量（WA，WB， WC，WD）; 以及基于序列输出向量（WA，WB，WC，WD）的值和延迟引起的延迟来确定模拟信号（S）跨越预定电压阈值（VA，VB，VC，VD）的时间 延迟元件（21,22,23）。

公开(公告)号：WO2015028594A1

公开(公告)日：2015-03-05

申请号：PCT/EP2014/068352

申请日：2014-08-29

Applicant: UNIWERSYTET JAGIELLONSKI

Inventor： KORCYL, Grzegorz ,  MOSKAL, Pawel ,  KAJETANOWICZ, Marcin ,  PALKA, Marek

IPC: G01T1/29

CPC classification number: G01T1/2985

Abstract: A system for acquisition of tomographic measurement data from measurement signals (S) of positron emission tomography (PET) or single-photon emission computed tomography (SPECT) detectors, the system comprising: a front-end electronic assembly (2) configured to convert the measurement signals (S) into digital and analog signals (DAS); a measurement electronics assembly (3) comprising time to digital converter (TDC) modules (31) configured to determine times (T) of pulses in digital signals (DS). The measurement electronics assembly (30) comprises: a series (TDCa-TDCd) of TDC modules (31), each module comprising a series (TDC1-TDC4) of TDC circuits (311 -314); a module controller (315) configured to transmit a clock signal (CLK), input to the module controller (315) from a system controller (40), to each of the TDC circuits (311-314); wherein each of the TDC circuits (311-314) is configured to execute measurements in a measurement window delimited by the neighboring edges of the clock signal (CLK) which is common for all TDC circuits (311-314).

Abstract translation: 一种用于从正电子发射断层摄影（PET）或单光子发射计算机断层摄影（SPECT）检测器的测量信号（S）获取断层摄影测量数据的系统，所述系统包括：前端电子组件（2） 测量信号（S）转换成数字和模拟信号（DAS）; 包括被配置为确定数字信号（DS）中的脉冲的时间（T））的时间到数字转换器（TDC）模块（31）的测量电子组件（3）。 测量电子组件（30）包括：TDC模块（31）的一系列（TDCa-TDCd），每个模块包括TDC电路（311-314）的一系列（TDC1-TDC4）; 模块控制器（315），被配置为从系统控制器（40）向每个所述TDC电路（311-314）发送从所述模块控制器（315）输入的时钟信号（CLK）。 其中每个TDC电路（311-314）被配置为在由所有TDC电路（311-314）共用的时钟信号（CLK）的相邻边界界定的测量窗口中执行测量。