Vertical 1 T-l R memory cells, memory arrays of vertical 1 T-1 R memory calls, and methods of forming such memory cells and memory arrays are described. The memory cells each include a vertical transistor (T) and a resistivity-switching element (R) coupled in series with and disposed above or below the vertical transistor. The vertical transistor includes a controlling electrode (G) coupled to a word line (WL) that is above or below the vertical transistor. The controlling electrode is disposed on a sidewall of the vertical transistor. Each vertical transistor (T) includes a first terminal coupled to a bit line (BL), a second terminal comprising the controlling electrode (G) coupled to a word line (WL), and a third terminal coupled to the resistivity-switching element (R).