公开(公告)号：WO2016053533A1

公开(公告)日：2016-04-07

申请号：PCT/US2015/047626

申请日：2015-08-30

Applicant: SANDISK 3D LLC

Inventor： SIAU, Chang ,  LEE, Jeffrey Koon Yee ,  YAN, Tianhong ,  CHEN, Yingchang ,  BALAKRISHNAN, Gopinath ,  LIU, Tz-Yi

IPC: G11C11/16 ,  G11C13/00 ,  G11C16/28 ,  G11C16/32

CPC classification number: G11C13/004 ,  G11C13/0028 ,  G11C13/0061 ,  G11C16/28 ,  G11C16/32 ,  G11C27/02 ,  G11C2013/0054

Abstract: A method is provided for reading a hard bit and N soft bits of a memory cell of a nonvolatile memory system in response to a single read command in a total time corresponding to a single read latency period and N + 1 data transfer times, the method comprising: generating a sense signal proportional to a current of the memory cell; generating a reference signal that comprises 2N + 1 distinct reference signal values; generating a comparison signal by comparing the sense signal and the reference signal; sampling the comparison signal to generate 2N + 1 data values; and determining the hard bit and the N soft bits based on the 2N + 1 data values.

Abstract translation: 提供了一种用于在对应于单个读等待时间周期和N + 1个数据传送时间的总时间内响应于单个读取命令来读取非易失性存储器系统的存储器单元的硬比特和N个软比特的方法，该方法 包括：产生与所述存储器单元的电流成比例的感测信号; 生成包括2N + 1个不同参考信号值的参考信号; 通过比较感测信号和参考信号来产生比较信号; 对比较信号进行采样以产生2N + 1个数据值; 以及基于2N + 1个数据值来确定硬比特和N个软比特。

公开(公告)号：WO2015148399A1

公开(公告)日：2015-10-01

申请号：PCT/US2015/022060

申请日：2015-03-23

Applicant: SANDISK 3D LLC

Inventor： YAN, Tianhong ,  SCHEUERLEIN, Roy E.

IPC: H01L27/24

CPC classification number: G11C13/0021 ,  G11C5/025 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/249

Abstract: A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements are each accessible by a word line (WL) in a plane and a local bit line. The three-dimensional array includes a two-dimensional array of pillar lines (331, 332) through the multiple layers of planes. The pillar lines are of a first type (331) that act as local bit lines and a second type (332) that provide access to the word lines by having respective memory elements (348) preset to a permanently low resistance state for connecting second-type pillar lines for exclusive access to respective word lines. An array of metal lines on the substrate is switchably connected to the vertical bit lines to provide access to the local bit lines and the word lines.

Abstract translation: 存储元件的三维阵列形成在位于半导体衬底上方不同距离的多个平面层上。 存储器元件各自可以通过平面中的字线（WL）和本地位线来访问。 三维阵列包括穿过多层平面的柱线（331,332）的二维阵列。 柱线是用作局部位线的第一类型（331）和第二类型（332），其通过将各自的存储元件（348）预设为永久低电阻状态来提供对字线的访问， 用于专用于相应字线的支柱线。 衬底上的金属线阵列可切换地连接到垂直位线以提供对局部位线和字线的访问。

公开(公告)号：WO2015069524A1

公开(公告)日：2015-05-14

申请号：PCT/US2014/062951

申请日：2014-10-29

Applicant: SANDISK 3D LLC

Inventor： PETTI, Christopher, J.

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  G11C13/0002 ,  H01L21/823487 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1675

Abstract: Vertical 1 T-l R memory cells, memory arrays of vertical 1 T-1 R memory calls, and methods of forming such memory cells and memory arrays are described. The memory cells each include a vertical transistor (T) and a resistivity-switching element (R) coupled in series with and disposed above or below the vertical transistor. The vertical transistor includes a controlling electrode (G) coupled to a word line (WL) that is above or below the vertical transistor. The controlling electrode is disposed on a sidewall of the vertical transistor. Each vertical transistor (T) includes a first terminal coupled to a bit line (BL), a second terminal comprising the controlling electrode (G) coupled to a word line (WL), and a third terminal coupled to the resistivity-switching element (R).

Abstract translation: 描述了垂直1 T-1 R存储器单元，垂直1 T-1 R存储器调用的存储器阵列，以及形成这种存储器单元和存储器阵列的方法。 每个存储单元包括垂直晶体管（T）和与垂直晶体管串联连接并设置在垂直晶体管上方或下方的电阻率开关元件（R）。 垂直晶体管包括耦合到垂直晶体管的上方或下方的字线（WL）的控制电极（G）。 控制电极设置在垂直晶体管的侧壁上。 每个垂直晶体管（T）包括耦合到位线（BL）的第一端子，包括耦合到字线（WL）的控制电极（G）的第二端子和耦合到电阻率开关元件 R）。

公开(公告)号：WO2015038557A1

公开(公告)日：2015-03-19

申请号：PCT/US2014/054864

申请日：2014-09-09

Applicant: SANDISK 3D LLC

Inventor： BANDYOPADHYAY, Abhijit ,  SCHEUERLEIN, Roy E. ,  GORLA, Chandrasekhar R. ,  LE, Brian

IPC: G11C13/00 ,  H01L27/24

CPC classification number: G11C13/0059 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/148

Abstract: Non-volatile storage devices having reversible resistance storage elements are disclosed herein. In one aspect, a memory cell unit includes one or more memory cells and a transistor (e.g., FET) that is used to control (e.g., limit) current of the memory cells. The drain of the transistor may be connected to a first end of the memory cell. If the memory cell unit has multiple memory cells then the drain may be connected to a node that is common to a first end of each of the memory cells. The source of the transistor is connected to a common source line. The gate of the transistor may be connected to a word line. The same word line may connect to the transistor gate of several (or many) different memory cell units. A second end of the memory cell is connected to a bit line.

Abstract translation: 本文公开了具有可逆电阻存储元件的非易失性存储装置。 在一个方面，存储单元单元包括一个或多个存储器单元和用于控制（例如，限制）存储器单元的电流的晶体管（例如，FET）。 晶体管的漏极可以连接到存储器单元的第一端。 如果存储单元单元具有多个存储器单元，则漏极可以连接到每个存储器单元的第一端公用的节点。 晶体管的源极连接到公共源极线。 晶体管的栅极可以连接到字线。 相同的字线可以连接到几个（或许多）不同存储单元单元的晶体管栅极。 存储单元的第二端连接到位线。

公开(公告)号：WO2015035038A1

公开(公告)日：2015-03-12

申请号：PCT/US2014/054080

申请日：2014-09-04

Applicant: SANDISK 3D LLC

Inventor： RABKIN, Peter ,  HIGASHITANI, Masaaki

IPC: G11C13/00 ,  H01L29/786 ,  H01L27/24

CPC classification number: H01L27/2454 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/0033 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/02403 ,  H01L21/02565 ,  H01L27/124 ,  H01L27/1259 ,  H01L27/127 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78642 ,  H01L29/7869 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/10 ,  H01L45/1226 ,  H01L45/1266 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149 ,  H01L45/16

Abstract: A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a body formed from a wide energy band gap semiconductor is disclosed. The wide energy band gap semiconductor may be an oxide semiconductor, such as a metal oxide semiconductor. As examples, this could be an InGaZnO, InZnO, HflnZnO, or ZnlnSnO body. The source and drains can also be formed from the wide energy band gap semiconductor, although these may be doped for better conduction. The vertically oriented TFT selection device serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device has a high drive current, a high breakdown voltage and low leakage current.

Abstract translation: 公开了具有由宽能带隙半导体形成的主体的垂直取向的薄膜晶体管（TFT）选择装置的3D存储器阵列。 宽能带隙半导体可以是诸如金属氧化物半导体的氧化物半导体。 例如，这可以是InGaZnO，InZnO，HflnZnO或ZnInSnO体。 源极和漏极也可以由宽能带隙半导体形成，尽管这些可以被掺杂以便更好地传导。 垂直取向的TFT选择装置用作3D存储器阵列中的垂直位线选择装置。 垂直TFT选择装置具有高驱动电流，高击穿电压和低漏电流。

公开(公告)号：WO2014200776A1

公开(公告)日：2014-12-18

申请号：PCT/US2014/040925

申请日：2014-06-04

Applicant: SANDISK 3D LLC

Inventor： CERNEA, Raul-Adrian

IPC: G11C7/06 ,  G11C16/28

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C2207/063

Abstract: The selected bit line in a non-volatile memory carries a cell conduction current to be measured and also a leakage current or noise due to weak coupling with neighboring array structures. In in a first phase, a sense amplifier senses the bit line current by discharging a capacitor with the combined current (cell conduction current plus the leakage current) over a predetermined time. In a second phase, the cell conduction current is minimized and significantly the leakage current in the selected bit line is used to recharge in tandem the capacitor in a time same as the predetermined time, effectively substracting the component of the leakage current measured in the first sensing phase. The resultant voltage drop on the capacitor over the two sensing phases provides a measure of the cell conduction current alone, thereby avoiding reading errors due to the leakage current present in the selected bit line.

Abstract translation: 非易失性存储器中所选择的位线携带要测量的单元传导电流，以及由于与相邻阵列结构的弱耦合而引起的漏电流或噪声。 在第一阶段中，感测放大器通过在预定时间内以组合电流（单元传导电流加上漏电流）放电电容器来感测位线电流。 在第二阶段，电池导通电流被最小化，并且显着地，使用所选位线中的漏电流在与预定时间相同的时间内串联电容器，从而有效地减去在第一个中测量的漏电流的分量 检测阶段。 两个感测相位上的电容器上产生的电压降提供了单独的电池导通电流的量度，从而避免了由于存在于所选位线中的泄漏电流而导致的读取误差。

公开(公告)号：WO2014159629A1

公开(公告)日：2014-10-02

申请号：PCT/US2014/024500

申请日：2014-03-12

Applicant: KABUSHIKI KAISHA TOSHIBA ,  SANDISK 3D LLC ,  INTERMOLECULAR, INC.

Inventor： WANG, Yun ,  GOPAL, Vidyut ,  HSUEH, Chien-Lan

IPC: H01L45/00

CPC classification number: H01L45/10 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/77 ,  H01L45/08 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A stack including a defect source layer, a defect blocking layer, and a defect acceptor layer disposed between the defect source layer and the defect blocking layer may be subjected to annealing. During the annealing, defects are transferred in a controllable manner from the defect source layer to the defect acceptor layer. At the same time, the defects are not transferred into the defect blocking layer thereby creating a lowest concentration zone within the defect acceptor layer. This zone is responsible for resistive switching. The precise control over the size of the zone and the defect concentration within the zone allows substantially improvement of resistive switching characteristics of the ReRAM cell. In some embodiments, the defect source layer includes aluminum oxynitride, the defect blocking layer includes titanium nitride, and the defect acceptor layer includes aluminum oxide.

Abstract translation: 提供了电阻随机存取存储器（ReRAM）单元及其制造方法。 可以对包括缺陷源层，缺陷阻挡层和设置在缺陷源层和缺陷阻挡层之间的缺陷受主层的堆叠进行退火。 在退火过程中，缺陷以可控的方式从缺陷源层转移到缺陷受体层。 同时，缺陷不会转移到缺陷阻挡层中，从而在缺陷受体层内形成最低浓度区。 该区域负责电阻交换。 精确控制区域的尺寸和区域内的缺陷浓度允许ReRAM单元的电阻开关特性得到显着改善。 在一些实施例中，缺陷源层包括氮氧化铝，缺陷阻挡层包括氮化钛，缺陷受主层包括氧化铝。

公开(公告)号：WO2014150985A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/024707

申请日：2014-03-12

Applicant: KABUSHIKI KAISHA TOSHIBA ,  SANDISK 3D LLC ,  INTERMOLECULAR, INC.

Inventor： TENDULKAR, Mihir ,  HIGUCHI, Randall ,  HSUEH, Chien-Lan

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/165 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L45/1625

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and resistive switching layer connected in series. The embedded resistor prevents excessive electrical currents through the resistive switching layer, especially when the resistive switching layer is switched into its low resistive state, thereby preventing over-programming. The embedded resistor includes aluminum, nitrogen, and one or more additional metals (other than aluminum). The concentration of each component is controlled to achieve desired resistivity and stability of the embedded resistor. In some embodiments, the resistivity ranges from 0.1 Ohm-centimeter to 40 Ohm- centimeter and remains substantially constant while applying an electrical field of up 8 mega-Volts /centimeter to the embedded resistor. The embedded resistor may be made from an amorphous material, and the material is operable to remain amorphous even when subjected to typical annealing conditions.

Abstract translation: 提供了电阻随机存取存储器（ReRAM）单元及其制造方法。 ReRAM单元包括串联连接的嵌入式电阻和电阻开关层。 嵌入式电阻器阻止通过电阻开关层的过多电流，特别是当电阻式开关层切换到其低电阻状态时，从而防止过度编程。 嵌入式电阻器包括铝，氮和一种或多种另外的金属（除铝以外）。 控制每个组分的浓度以实现嵌入式电阻器的期望的电阻率和稳定性。 在一些实施例中，电阻率范围为0.1欧姆至40欧姆厘米，并且在施加高达8兆伏特/厘米的电场到嵌入式电阻器时保持基本恒定。 嵌入式电阻器可以由非晶材料制成，并且即使经受典型的退火条件，该材料也可操作以保持非晶态。

公开(公告)号：WO2014137847A1

公开(公告)日：2014-09-12

申请号：PCT/US2014/019736

申请日：2014-03-01

Applicant: SANDISK 3D LLC

Inventor： YAP, Kian-Chin Alex

IPC: G11C16/26 ,  G11C16/32 ,  G11C7/10 ,  G11C7/22

CPC classification number: G06F12/0246 ,  G06F12/0862 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2272 ,  G11C2207/2281

Abstract: An asynchronous FIFO buffer that provides data in response to requests to read a memory array is disclosed. The asynchronous FIFO buffer provides the data output within a latency tolerance. The asynchronous FIFO has a read clock input and a write clock input. The read clock input receives a read enable signal that defines how data should be clocked out. The write clock input receives a write clock that is asynchronous from the read enable signal. The asynchronous FIFO inputs data from the memory array in accordance with the write clock signal. The asynchronous FIFO outputs data in accordance with the read enable signal. Control logic may pre-fetch data from the memory array into the asynchronous FIFO prior to the read enable signal first being received.

Abstract translation: 公开了一种响应于读取存储器阵列的请求而提供数据的异步FIFO缓冲器。 异步FIFO缓冲器在延迟容差内提供数据输出。 异步FIFO具有读时钟输入和写时钟输入。 读时钟输入接收一个读使能信号，该信号定义数据应如何计时。 写时钟输入接收与读使能信号异步的写时钟。 异步FIFO根据写时钟信号从存储器阵列输入数据。 异步FIFO根据读使能信号输出数据。 在首先接收到读使能信号之前，控制逻辑可以将数据从存储器阵列预取到异步FIFO中。

公开(公告)号：WO2014137652A3

公开(公告)日：2014-09-12

申请号：PCT/US2014/018125

申请日：2014-02-25

Applicant: SANDISK 3D LLC

Inventor： RABKIN, Peter ,  HIGASHITANI, Masaaki

IPC: H01L27/24 ,  H01L29/786 ,  H01L27/105 ,  H01L27/115 ,  G11C13/00 ,  H01L45/00

Abstract: A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a channel extension, otherwise referred to as a gate/junction offset, is disclosed. The vertically oriented TFT selection device with channel extension serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device having a channel extension has a high breakdown voltage and low leakage current. The channel extension can be at the top junction or bottom junction of the TFT. Depending on whether the memory elements undergo a forward FORM or reverse FORM, either the bottom or top junction can have the channel extension. This provides for a high voltage junction where needed.