Invention Application
WO2016105350A1 METHOD AND STRUCTURE TO CONTACT TIGHT PITCH CONDUCTIVE LAYERS WITH GUIDED VIAS USING ALTERNATING HARDMASKS AND ENCAPSULATING ETCHSTOP LINER SCHEME
审中-公开
使用替代硬件和封装ETCHSTOP LINER程序与引导VIAS接触的垂直导引层的方法和结构
- Patent Title: METHOD AND STRUCTURE TO CONTACT TIGHT PITCH CONDUCTIVE LAYERS WITH GUIDED VIAS USING ALTERNATING HARDMASKS AND ENCAPSULATING ETCHSTOP LINER SCHEME
- Patent Title (中): 使用替代硬件和封装ETCHSTOP LINER程序与引导VIAS接触的垂直导引层的方法和结构
-
Application No.: PCT/US2014/071999Application Date: 2014-12-22
-
Publication No.: WO2016105350A1Publication Date: 2016-06-30
- Inventor: CHAWLA, Jasmeet S. , BRAIN, Ruth A. , SCHENKER, Richard E. , SINGH, Kanwal Jit , MYERS, Alan M.
- Applicant: INTEL CORPORATION
- Applicant Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Agency: BLANK, Eric S. et al.
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/31
Abstract:
Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.
Information query
IPC分类: