公开(公告)号：WO2015094488A1

公开(公告)日：2015-06-25

申请号：PCT/US2014/063128

申请日：2014-10-30

Applicant: INTEL CORPORATION

Inventor： BRISTOL, Robert L. ,  BLACKWELL, James M. ,  MYERS, Alan M. ,  SINGH, Kanwal J.

IPC: H01L21/768 ,  H01L21/60

CPC classification number: H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. A second layer of the interconnect structure is disposed above the first layer of the interconnect structure. Dielectric lines of the second grating overlap and contact, but are distinct from, dielectric lines of the first grating. First and second dielectric regions are disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The first dielectric region is composed of a first cross-linked photolyzable material, and the second dielectric region is composed of a second, different, cross-linked photolyzable material.

Abstract translation: 描述了通过用于后端（BEOL）互连的多色photobuckets图案化的自对准。 在一个示例中，用于集成电路的互连结构包括设置在基板上方的互连结构的第一层。 互连结构的第二层设置在互连结构的第一层之上。 第二光栅的介电线与第一光栅的介质线重叠和接触，但不同。 第一和第二电介质区域设置在第一光栅的金属线和第二光栅的金属线之间，并且在与第一光栅的介质线的上部和第二栅的介电线的下部相同的平面中 光栅。 第一电介质区域由第一交联光可光化材料组成，第二电介质区域由第二不同的交联光可光化材料组成。

公开(公告)号：WO2016105350A1

公开(公告)日：2016-06-30

申请号：PCT/US2014/071999

申请日：2014-12-22

Applicant: INTEL CORPORATION

Inventor： CHAWLA, Jasmeet S. ,  BRAIN, Ruth A. ,  SCHENKER, Richard E. ,  SINGH, Kanwal Jit ,  MYERS, Alan M.

IPC: H01L21/768 ,  H01L21/31

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/485 ,  H01L21/486 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2224/16225

Abstract: Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.

Abstract translation: 描述了具有交替电介质盖的互连结构和用于半导体器件的蚀刻衬垫以及用于制造这种器件的方法。 根据实施例，互连结构可以包括在ILD的顶表面上方的第一硬掩模层的层间电介质（ILD）。 互连结构还可以包括ILD中的一个或多个第一互连线。 第一电介质盖可以位于每个第一互连线的顶表面上方。 另外的实施例包括ILD中以与第一互连线交替模式布置的一个或多个第二互连线。 第二电介质盖可以形成在每个第二互连线的顶表面之上。 实施例还可以包括形成在第一电介质盖的顶表面上的蚀刻阻挡衬里。

公开(公告)号：WO2016105344A1

公开(公告)日：2016-06-30

申请号：PCT/US2014/071909

申请日：2014-12-22

Applicant: INTEL CORPORATION

Inventor： SINGH, Kanwal Jit ,  MYERS, Alan M.

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/7682 ,  H01L21/764 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L29/78 ,  H01L2224/16225

Abstract: A method including forming a sacrificial material between metal lines of an integrated circuit structure; forming a mask on the sacrificial material; and after forming the mask, removing the sacrificial material to leave a void between the metal lines. An apparatus including an integrated circuit substrate; a first metallization level on the substrate; a second metallization; and a mask disposed between the first metallization level and the second metallization level, the mask including a dielectric material having a porosity select to allow mass transport therethrough, wherein each of the first metallization level and the second metallization level comprises a plurality of metal lines and a portion of adjacent metal lines of at least one of the first metallization level and the second metallization level are separated by voids.

Abstract translation: 一种包括在集成电路结构的金属线之间形成牺牲材料的方法; 在牺牲材料上形成掩模; 并且在形成掩模之后，去除牺牲材料以在金属线之间留下空隙。 一种包括集成电路基板的装置; 在衬底上的第一金属化水平; 第二次金属化; 以及设置在所述第一金属化层和所述第二金属化层之间的掩模，所述掩模包括具有孔隙率选择以允许质量传输通过其中的电介质材料，其中所述第一金属化层和所述第二金属化层中的每一个包括多个金属线和 第一金属化层和第二金属化层中的至少一个的相邻金属线的一部分被空隙分开。

公开(公告)号：WO2016209293A1

公开(公告)日：2016-12-29

申请号：PCT/US2015/038145

申请日：2015-06-26

Applicant: INTEL CORPORATION ,  LIN, Kevin ,  BRISTOL, Robert Lindsey ,  MYERS, Alan M.

Inventor： LIN, Kevin ,  BRISTOL, Robert Lindsey ,  MYERS, Alan M.

IPC: H01L21/027

CPC classification number: H01L21/32139 ,  H01L21/0334 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226

Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmaskS. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.

Abstract translation: 本发明的实施例包括形成织物图案化硬掩模的方法。 在一个实施例中，第一硬掩模和第二硬掩模以交替图案形成在互连层的顶表面上。 然后可以在第一和第二硬掩模S上形成牺牲交叉光栅。 在一个实施例中，去除未被牺牲交叉光栅覆盖的第一硬掩模的部分以形成第一开口，并且将第三硬掩模设置在第一开口中。 实施例可以包括蚀刻通过未被牺牲交叉光栅覆盖的第二硬掩模的部分以形成第二开口。 第二开口可以填充第四硬掩模。 根据实施例，第一，第二，第三和第四硬掩模是相互蚀刻选择性的。 在一个实施例中，可以去除牺牲交叉光栅。

公开(公告)号：WO2015112272A1

公开(公告)日：2015-07-30

申请号：PCT/US2014/069355

申请日：2014-12-09

Applicant: INTEL CORPORATION

Inventor： JEZEWSKI, Christopher J. ,  CHAWLA, Jasmeet S. ,  SINGH, Kanwal Jit ,  MYERS, Alan M. ,  TAN, Eliot N. ,  SCHENKER, Richard E.

IPC: H01L21/768 ,  H01L21/31

CPC classification number: H01L21/7688 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76886 ,  H01L21/76897 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to formed interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminated the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allows for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.

Abstract translation: 用于形成在电介质层内具有紧密间距互连结构的互连层的工艺，其中用于形成的互连结构的沟槽和通孔在金属化之前具有相对低的纵横比。 当沉积时，低纵横比可以减少或基本上消除在金属化材料内形成的空隙的电位。 本文的实施例可以通过允许在金属化之前去除用于形成沟槽和通孔的结构的工艺来实现这种相对低的纵横比。

公开(公告)号：WO2015094502A1

公开(公告)日：2015-06-25

申请号：PCT/US2014/064156

申请日：2014-11-05

Applicant: INTEL CORPORATION

Inventor： MYERS, Alan M. ,  SINGH, Kanwal Jit ,  BRISTOL, Robert L. ,  CHAWLA, Jasmeet S.

IPC: H01L21/768 ,  H01L21/31 ,  H01L21/60

CPC classification number: H01L23/5226 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer.

Abstract translation: 描述了使用对角线硬掩模进行自对准通孔和插头图案，以便制造后端（BEOL）互连的改进覆盖。 在一个示例中，制造用于集成电路的互连结构的方法包括在布置在衬底上方的层间介电层上形成第一硬掩模层。 第一硬掩模层包括多个第一硬掩模线，其具有在第一方向上的第一光栅，并且包括与第一光栅交错的一个或多个牺牲材料。 该方法还涉及在第一硬掩模层之上形成第二硬掩模层。 第二硬掩模层包括多个第二硬掩模线，所述第二硬掩模线在第二方向上具有与第一方向对角的第二光栅。 该方法还涉及使用第二硬掩模层作为掩模，蚀刻第一硬掩模层以形成图案化的第一硬掩模层。