Invention Application
- Patent Title: MIDDLE-OF-LINE INTEGRATION METHODS AND SEMICONDUCTOR DEVICES
- Patent Title (中): 中间集成方法和半导体器件
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Application No.: PCT/US2016/015923Application Date: 2016-02-01
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Publication No.: WO2016130350A1Publication Date: 2016-08-18
- Inventor: ZHU, John Jianhong , YANG, Da , XU, Jeffrey Junhao , SONG, Stanley Seungchul , RIM, Kern
- Applicant: QUALCOMM INCORPORATED
- Applicant Address: 5775 Morehouse Drive San Diego, California 92121-1714 US
- Assignee: QUALCOMM INCORPORATED
- Current Assignee: QUALCOMM INCORPORATED
- Current Assignee Address: 5775 Morehouse Drive San Diego, California 92121-1714 US
- Agency: TOLER, Jeffrey G.
- Priority: US14/622,516 20150213
- Main IPC: H01L21/8238
- IPC: H01L21/8238
Abstract:
An electronic device includes a middle-of-line (MOL) stack. The electronic device includes a top local interconnect layer and a contact coupling the top local interconnect layer to a gate of a semiconductor device through a first dielectric layer. The electronic device also includes one or more isolation walls between the contact and the first dielectric layer, wherein the one or more isolation walls include aluminum nitride (AlN).
Information query
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