公开(公告)号：WO2016133837A1

公开(公告)日：2016-08-25

申请号：PCT/US2016/017936

申请日：2016-02-15

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Stanley Seungchul ,  XU, Jeffrey Junhao ,  YANG, Da ,  YEAP, Choh Fei

IPC: G03F7/20 ,  G03F1/00

CPC classification number: H01L21/76802 ,  G03F1/14 ,  G03F7/203 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/7045 ,  G03F7/70466 ,  G06F17/5077 ,  H01L21/31116 ,  H01L23/535

Abstract: Electron-beam (e-beam) based semiconductor device features are disclosed. In a particular aspect, a method includes performing a first lithography process to fabricate a first set of cut pattern features on a semiconductor device. A distance of each feature of the first set of cut pattern features from the feature to an active area is greater than or equal to a threshold distance. The method further includes performing an electron-beam (e-beam) process to fabricate a second cut pattern feature on the semiconductor device. A second distance of the second cut pattern feature from the second cut pattern feature to the active area is less than or equal to the threshold distance.

Abstract translation: 公开了基于电子束（e-beam）的半导体器件特征。 在特定方面，一种方法包括执行第一光刻工艺以在半导体器件上制造第一组切割图案特征。 从特征到有效区域的第一组切割图案特征的每个特征的距离大于或等于阈值距离。 该方法还包括执行电子束（e-beam）工艺以在半导体器件上制造第二切割图案特征。 第二切割图案特征从第二切割图案特征到有效区域的第二距离小于或等于阈值距离。

公开(公告)号：WO2016130350A1

公开(公告)日：2016-08-18

申请号：PCT/US2016/015923

申请日：2016-02-01

Applicant: QUALCOMM INCORPORATED

Inventor： ZHU, John Jianhong ,  YANG, Da ,  XU, Jeffrey Junhao ,  SONG, Stanley Seungchul ,  RIM, Kern

IPC: H01L21/8238

CPC classification number: H01L23/53295 ,  H01L21/02178 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/535

Abstract: An electronic device includes a middle-of-line (MOL) stack. The electronic device includes a top local interconnect layer and a contact coupling the top local interconnect layer to a gate of a semiconductor device through a first dielectric layer. The electronic device also includes one or more isolation walls between the contact and the first dielectric layer, wherein the one or more isolation walls include aluminum nitride (AlN).

Abstract translation: 电子设备包括中间线（MOL）堆叠。 电子器件包括顶部局部互连层和通过第一介电层将顶部局部互连层耦合到半导体器件的栅极的触点。 电子设备还包括在接触件和第一电介质层之间的一个或多个隔离壁，其中一个或多个隔离壁包括氮化铝（AlN）。

公开(公告)号：WO2015130549A2

公开(公告)日：2015-09-03

申请号：PCT/US2015/016621

申请日：2015-02-19

Applicant: QUALCOMM INCORPORATED

Inventor： XU, Jeffrey Junhao ,  ZHU, John Jianhong ,  YEAP, Choh Fei

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76831 ,  H01L21/76847 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer.

Abstract translation: 半导体器件包括具有将第一互连层耦合到沟槽的通孔的管芯。 半导体器件还包括在沟槽的侧壁和相邻表面上以及在通孔的侧壁上的阻挡层。 半导体器件在第一互连层的表面上具有掺杂的导电层。 掺杂导电层在通孔的侧壁之间延伸。 半导体器件还包括在通孔和沟槽中的阻挡层上的导电材料。 导电材料位于设置在第一互连层表面上的掺杂导电层上。

公开(公告)号：WO2015130507A1

公开(公告)日：2015-09-03

申请号：PCT/US2015/016081

申请日：2015-02-17

Applicant: QUALCOMM INCORPORATED

Inventor： XU, Jeffrey Junhao ,  YEAP, Choh Fei

IPC: H01L29/78 ,  H01L29/36

CPC classification number: H01L29/7849 ,  H01L21/02164 ,  H01L21/02238 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor fin is on a substrate, and extends in a longitudinal direction parallel to the substrate. The fin projects, in a vertical direction, to a fin top at a fin height above the substrate. An embedded fin stressor element is embedded in the fin. The fin stressor element is configured to urge a vertical compression force within the fin, parallel to the vertical direction. Optionally, the semiconductor material includes silicon, and embedded fin stressor element includes silicon dioxide.

Abstract translation: 半导体鳍片在基板上，并且在平行于基板的纵向方向上延伸。 翅片在垂直方向上突出到底板上方翅片高度的翅片顶部。 嵌入式翅片应力元件嵌入翅片。 翅片应力元件构造成促使平行于垂直方向的翅片内的垂直压缩力。 可选地，半导体材料包括硅，并且嵌入式翅片应力元件包括二氧化硅。

公开(公告)号：WO2016191407A1

公开(公告)日：2016-12-01

申请号：PCT/US2016/033876

申请日：2016-05-24

Applicant: QUALCOMM INCORPORATED

Inventor： BAO, Junjing ,  YANG, Haining ,  LIU, Yanxiang ,  XU, Jeffrey Junhao

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/495 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A sacrificial cap is grown on an upper surface of a conductor. A dielectric spacer is against a side of the conductor. An upper dielectric side spacer is formed on a sidewall of the sacrificial cap. The sacrificial cap is selectively etched, leaving a cap recess, and the upper dielectric side spacer facing the cap recess. Silicon nitride is filled in the cap recess, to form a center cap and a protective cap having center cap and the upper dielectric spacer.

Abstract translation: 在导体的上表面上生长牺牲帽。 电介质隔离物抵靠导体的一侧。 在绝缘帽的侧壁上形成上绝缘侧绝缘体。 牺牲帽被选择性地蚀刻，留下盖子凹槽，并且上电介质侧隔离物面向盖凹槽。 氮化硅填充在盖凹部中，以形成中心帽和具有中心帽和上部电介质间隔物的保护帽。

公开(公告)号：WO2016137589A1

公开(公告)日：2016-09-01

申请号：PCT/US2016/012893

申请日：2016-01-11

Applicant: QUALCOMM INCORPORATED

Inventor： MACHKAOUTSAN, Valdimir ,  BADAROGLU, Mustafa ,  XU, Jeffrey Junhao ,  SONG, Stanley Seungchul ,  YEAP, Choh Fei

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/775 ,  B82Y10/00

CPC classification number: H01L21/823828 ,  B82Y10/00 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit (IC) device includes a first nanowire GAA active transistor (810) of a first-type (N-Type) in a first-type region. The first active transistor may have a first-type work function material (824, NWFM) and a low channel dopant concentration in an active portion. The integrated circuit also includes a second nanowire GAA active transistor (810), using the same nanowire channel as the first active transistor. The IC device furthermore includes a first isolation transistor (TIE-OFF 840) of the first-type in the first- type region, sharing the nanowires of the first and second active nanowire GAA transistors. The first isolation transistor (TIE-OFF 840) is arranged between the first and second active transistors and has a workfunction (832 PWFM) opposite to that of the active transistors on the same nanowire. Further active transistors (P-type) may be arranged using parallel nanowires and may have a second-type work function material (834).

Abstract translation: 集成电路（IC）装置包括在第一类型区域中的第一类型（N型）的第一纳米线GAA有源晶体管（810）。 第一有源晶体管可以在有源部分中具有第一类功函数材料（824，NWFM）和低通道掺杂剂浓度。 集成电路还包括使用与第一有源晶体管相同的纳米线通道的第二纳米线GAA有源晶体管（810）。 IC器件还包括在第一类型区域中的第一类型的第一隔离晶体管（TIE-OFF 840），共享第一和第二有源纳米线GAA晶体管的纳米线。 第一隔离晶体管（TIE-OFF 840）布置在第一和第二有源晶体管之间，并且具有与相同纳米线上的有源晶体管相反的功函数（832 PWFM）。 可以使用平行的纳米线布置其它有源晶体管（P型），并且可以具有第二类型功函数材料（834）。

公开(公告)号：WO2016081160A1

公开(公告)日：2016-05-26

申请号：PCT/US2015/057369

申请日：2015-10-26

Applicant: QUALCOMM INCORPORATED

Inventor： BAO, Junjing ,  XU, Jeffrey Junhao ,  ZHU, John Jianhong ,  YANG, Da ,  SONG, Stanley Seungchul ,  YEAP, Choh Fei

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/32051 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76864 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a dielectric material and an interconnect structure. The semiconductor device further includes a barrier layer positioned between the dielectric material and the interconnect structure. The barrier layer includes two or more metals. Each metal of the two or more metals of the barrier layer is phase segregated from each other metal of the two or more metals.

Abstract translation: 半导体器件包括电介质材料和互连结构。 该半导体器件还包括位于介电材料和互连结构之间的阻挡层。 阻挡层包括两种或更多种金属。 阻挡层的两种或更多种金属的每种金属与两种或更多种金属的彼此金属相分离。

公开(公告)号：WO2016010699A1

公开(公告)日：2016-01-21

申请号：PCT/US2015/037529

申请日：2015-06-24

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Xia ,  XU, Jeffrey Junhao ,  LU, Xiao ,  YANG, Bin ,  YUAN, Jun ,  CHEN, Xiaonan ,  WANG, Zhongze

IPC: H01L27/112 ,  H01L29/51 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  G11C17/18 ,  H01L27/11206 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517

Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.

Abstract translation: 一种装置包括金属栅极，衬底材料和金属栅极和衬底材料之间的氧化物层。 氧化物层包括与金属栅极接触的氧化铪层和与衬底材料接触并与氧化铪层接触的二氧化硅层。 金属栅极，衬底材料和氧化物层包括在一次性可编程（OTP）存储器件中。 OTP存储器件包括晶体管。 OTP存储器件的非易失性状态基于OTP存储器件的阈值电压偏移。

公开(公告)号：WO2015142438A2

公开(公告)日：2015-09-24

申请号：PCT/US2015/014857

申请日：2015-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： XU, Jeffrey Junhao ,  RIM, Kern ,  ZHU, John Jianhong ,  SONG, Stanley Seungchul ,  YEAP, Choh Fei

IPC: H01L21/285

CPC classification number: H01L21/823814 ,  C23C14/24 ,  C23C14/54 ,  C23C16/46 ,  C23C16/52 ,  H01L21/285 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/324 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66568

Abstract: A method includes forming a first metal layer on source/drain regions of an n-type metal-oxide-semiconductor (NMOS) device and on source/drain regions of a p-type MOS (PMOS) device by chemical vapor deposition (CVD) or non-energetic physical vapor deposition (PVD). The method further includes selectively performing a rapid thermal anneal (RTA) process on the first metal layer after forming the first metal layer.

Abstract translation: 一种方法包括通过化学气相沉积（CVD）在n型金属氧化物半导体（NMOS）器件的源极/漏极区域和p型MOS（PMOS）器件的源极/漏极区域上形成第一金属层， 或非能量物理气相沉积（PVD）。 该方法还包括在形成第一金属层之后在第一金属层上选择性地执行快速热退火（RTA）工艺。

公开(公告)号：WO2015102753A1

公开(公告)日：2015-07-09

申请号：PCT/US2014/065529

申请日：2014-11-13

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Stanley Seungchul ,  RIM, Kern ,  WANG, Zhongze ,  XU, Jeffrey Junhao ,  CHEN, Xiangdong ,  YEAP, Choh Fei

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76814 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating middle of line (MOL) layers and devices including MOL layers. A method in accordance with an aspect of the present disclosure includes depositing a hard mask (500) across active contacts (112) to terminals of semiconductor devices of a semiconductor substrate. Such a method also includes patterning the hard mask to selectively expose some of the active contacts (112-5) and selectively insulate some of the active contacts (112-2). The method also includes depositing a conductive material (1100) on the patterned hard mask and the exposed active contacts to couple the exposed active contacts to each other over an active area of the semiconductor devices.

Abstract translation: 制造中间线（MOL）层和包括MOL层的器件的方法。 根据本公开的一个方面的方法包括将半导体衬底的半导体器件的端子上的有源触点（112）沉积硬掩模（500）。 这种方法还包括图案化硬掩模以选择性地暴露一些有源触点（112-5）并且选择性地绝缘一些有源触点（112-2）。 该方法还包括在图案化的硬掩模和暴露的有源触点上沉积导电材料（1100），以在半导体器件的有效区域上将暴露的有源触点彼此耦合。