Invention Application
- Patent Title: A METHOD FOR CALIBRATING THE READ LATENCY OF A DDR DRAM MODULE
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Application No.: PCT/IN2016/000152Application Date: 2016-06-13
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Publication No.: WO2016203490A3Publication Date: 2016-12-22
- Inventor: GYAN, Prakash , NIDHIR, Kumar , CHANDRASHEKAR, Narla
- Applicant: GYAN, Prakash , NIDHIR, Kumar , CHANDRASHEKAR, Narla
- Applicant Address: H.NO. 228, Birsa Chowk, Birsa Nagar Khunti Road (Bank of India Lane) Hatia Ranchi - 834003, Jharkand IN
- Assignee: GYAN, Prakash,NIDHIR, Kumar,CHANDRASHEKAR, Narla
- Current Assignee: GYAN, Prakash,NIDHIR, Kumar,CHANDRASHEKAR, Narla
- Current Assignee Address: H.NO. 228, Birsa Chowk, Birsa Nagar Khunti Road (Bank of India Lane) Hatia Ranchi - 834003, Jharkand IN
- Agency: PRABHU, Rakesh
- Priority: IN1278/CHE/2015 20150616
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/28
Abstract:
A method for automatic calibration of read latency of a memory module is envisaged. The read latency is initially set to a default maximum value. The default maximum value is equivalent to the number of clock cycles required to complete a data read operation. A data pattern to be read from the memory module in consideration of the default maximum value is identified. A memory read operation is preformed, and a first data pattern is captured, in accordance with the default maximum value. The identified data pattern is compared with the first data pattern, and the default maximum value is iteratively calibrated based on the comparison thereof. Aforementioned steps are repeated across a plurality of memory read operations, and variations in the maximum default value are tracked, and an average maximum value is calculated based thereupon. The average maximum value is assigned as the read latency for the memory module.
Public/Granted literature
- WO2016203490A2 A METHOD FOR CALIBRATING THE READ LATENCY OF A DDR DRAM MODULE Public/Granted day:2016-12-22
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