公开(公告)号：WO2017006339A2

公开(公告)日：2017-01-12

申请号：PCT/IN2016/000170

申请日：2016-06-30

Applicant: GYAN, Prakash ,  NIDHIR, Kumar

Inventor： GYAN, Prakash ,  NIDHIR, Kumar ,  MUNISWARA REDDY VORUGU

IPC: H03L7/00

CPC classification number: H03L7/00 ,  G06F1/04 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/06 ,  H03L7/0814

Abstract: A system and method for aligning clock signals in a DDR DRAM module is disclosed. The system includes a phase detector circuitry, a controllable delay circuit, a first delay circuit and a synchronizing circuit. A clock signal is simultaneously transmitted through the first delay circuit and the controllable delay circuit. Subsequently, the clock signals transmitted through the first delay circuit and the controllable delay circuit are captured at the output thereof, and fed as inputs to the phase detector circuitry. The phase detector circuitry determines whether the clock signals are in phase, and accordingly adjusts the delay associated with the controllable delay circuit until the two clock signals are determined to be in phase.

Abstract translation: 公开了一种用于在DDR DRAM模块中对齐时钟信号的系统和方法。 该系统包括相位检测器电路，可控延迟电路，第一延迟电路和同步电路。 时钟信号通过第一延迟电路和可控延迟电路同时发送。 随后，通过第一延迟电路和可控延迟电路传输的时钟信号在其输出端被捕获，并且作为输入被馈送到相位检测器电路。 相位检测器电路确定时钟信号是否同相，并相应地调整与可控延迟电路相关的延迟，直到两个时钟信号被确定为同相为止。

公开(公告)号：WO2016203491A2

公开(公告)日：2016-12-22

申请号：PCT/IN2016/000154

申请日：2016-06-14

Applicant: GYAN, Prakash ,  NIDHIR, Kumar

Inventor： GYAN, Prakash ,  NIDHIR, Kumar

IPC: H03K5/00

CPC classification number: H03K5/135 ,  H03K3/0375 ,  H03K19/0016

Abstract: The present disclosure envisages an asynchronous clock gating circuitry and a method for designing the asynchronous clock gating circuitry. The asynchronous clock gating circuitry could be placed at the very beginning of the clock network, given its design and implementation logic. The asynchronous clock gating circuitry helps meet the timing requirement on the enable pin thereof. The asynchronous clock gating circuitry avoids cumbersome replication of clock gating circuitry during physical implementation of the (circuit) design, and further helps reduce the power consumption levels in sequential circuits.

Abstract translation: 本公开设计了异步时钟门控电路和用于设计异步时钟门控电路的方法。 鉴于其设计和实现逻辑，异步时钟门控电路可以放置在时钟网络的开始处。 异步时钟门控电路有助于满足其使能引脚上的时序要求。 异步时钟门控电路避免了在（电路）设计的物理实现期间时钟门控电路的繁琐复制，并且进一步有助于降低时序电路中的功耗水平。

公开(公告)号：WO2016203490A3

公开(公告)日：2016-12-22

申请号：PCT/IN2016/000152

申请日：2016-06-13

Applicant: GYAN, Prakash ,  NIDHIR, Kumar ,  CHANDRASHEKAR, Narla

Inventor： GYAN, Prakash ,  NIDHIR, Kumar ,  CHANDRASHEKAR, Narla

IPC: G06F12/00 ,  G06F13/28

Abstract: A method for automatic calibration of read latency of a memory module is envisaged. The read latency is initially set to a default maximum value. The default maximum value is equivalent to the number of clock cycles required to complete a data read operation. A data pattern to be read from the memory module in consideration of the default maximum value is identified. A memory read operation is preformed, and a first data pattern is captured, in accordance with the default maximum value. The identified data pattern is compared with the first data pattern, and the default maximum value is iteratively calibrated based on the comparison thereof. Aforementioned steps are repeated across a plurality of memory read operations, and variations in the maximum default value are tracked, and an average maximum value is calculated based thereupon. The average maximum value is assigned as the read latency for the memory module.

公开(公告)号：WO2016203492A3

公开(公告)日：2016-12-22

申请号：PCT/IN2016/000155

申请日：2016-06-14

Applicant: GYAN, Prakash ,  NIDHIR, Kumar

Inventor： GYAN, Prakash ,  NIDHIR, Kumar

IPC: H04L7/02 ,  G06F11/00 ,  G06F1/04

Abstract: A method and system for cycle accurate data transfer between skewed source synchronous clocks is envisaged. The procedure starts through reset. On reset, both the write and read address registers are set to point to location 0. Source clock is stopped to disable active clock edges to both write and read address registers during the reset procedure. The source clock is subsequently started to deliver active edges to both write and read address registers. On every active source clock edge, data is pushed into the data register based on the location pointed by write address register. On every skewed active clock edge, data is read from the data register based on the address pointed by read address register. Due to the delayed nature of clock reaching the read address register, write address register increments first and stores data into the data register.

公开(公告)号：WO2016135744A3

公开(公告)日：2016-09-01

申请号：PCT/IN2016/000048

申请日：2016-02-24

Applicant: GYAN, Prakash ,  NIDHIR, Kumar

Inventor： GYAN, Prakash ,  NIDHIR, Kumar

IPC: G11C7/22 ,  G11C11/40

Abstract: A method and system for multi cycle write leveling are disclosed. At least three data patterns are written into consecutive address locations of a memory device via corresponding write operations. Subsequently, predetermined beats of data strobe signals corresponding to certain predetermined write operations are gated. Based at least on the gating of predetermined data beats, a target data pattern to be read from the memory device is determined. Subsequently, a data read operation is performed, and the data written onto a specific address location of the memory device is read there from. The data thus read from the memory device is compared with the target pattern. Based on the comparison of the data read from the memory device with the target pattern, a delay cycle between the data strobe signals and clock signal is determined, and the data strobe signal and clock signal are accordingly calibrated.

公开(公告)号：WO2017006339A3

公开(公告)日：2017-01-12

申请号：PCT/IN2016/000170

申请日：2016-06-30

Applicant: GYAN, Prakash ,  NIDHIR, Kumar

Inventor： GYAN, Prakash ,  NIDHIR, Kumar ,  MUNISWARA REDDY VORUGU

IPC: G06F1/12

Abstract: A system and method for aligning clock signals in a DDR DRAM module is disclosed. The system includes a phase detector circuitry, a controllable delay circuit, a first delay circuit and a synchronizing circuit. A clock signal is simultaneously transmitted through the first delay circuit and the controllable delay circuit. Subsequently, the clock signals transmitted through the first delay circuit and the controllable delay circuit are captured at the output thereof, and fed as inputs to the phase detector circuitry. The phase detector circuitry determines whether the clock signals are in phase, and accordingly adjusts the delay associated with the controllable delay circuit until the two clock signals are determined to be in phase.

公开(公告)号：WO2016135744A2

公开(公告)日：2016-09-01

申请号：PCT/IN2016/000048

申请日：2016-02-24

Applicant: GYAN, Prakash ,  NIDHIR, Kumar

Inventor： GYAN, Prakash ,  NIDHIR, Kumar

CPC classification number: G11C11/4076 ,  G11C5/04 ,  G11C8/18 ,  G11C11/4096 ,  G11C29/023 ,  G11C2207/2254

Abstract: A method and system for multi cycle write leveling are disclosed. At least three data patterns are written into consecutive address locations of a memory device via corresponding write operations. Subsequently, predetermined beats of data strobe signals corresponding to certain predetermined write operations are gated. Based at least on the gating of predetermined data beats, a target data pattern to be read from the memory device is determined. Subsequently, a data read operation is performed, and the data written onto a specific address location of the memory device is read there from. The data thus read from the memory device is compared with the target pattern. Based on the comparison of the data read from the memory device with the target pattern, a delay cycle between the data strobe signals and clock signal is determined, and the data strobe signal and clock signal are accordingly calibrated.

Abstract translation: 公开了一种用于多周期写入调平的方法和系统。 至少三个数据模式通过相应的写入操作被写入存储器件的连续地址位置。 随后，选择对应于某些预定写入操作的预定数量的选通脉冲信号。 至少基于预定数据节拍的门控，确定要从存储装置读取的目标数据模式。 随后，执行数据读取操作，并且从那里读取写入存储器件的特定地址位置的数据。 将从存储器件读出的数据与目标图案进行比较。 基于从存储器件读取的数据与目标图案的比较，确定数据选通信号和时钟信号之间的延迟周期，并相应地校准数据选通信号和时钟信号。

公开(公告)号：WO2016203492A2

公开(公告)日：2016-12-22

申请号：PCT/IN2016/000155

申请日：2016-06-14

Applicant: GYAN, Prakash ,  NIDHIR, Kumar

Inventor： GYAN, Prakash ,  NIDHIR, Kumar

IPC: G06F1/04

CPC classification number: G06F1/04 ,  G06F5/06 ,  G06F5/10 ,  G06F9/30134 ,  G06F2205/123 ,  G11C7/10 ,  G11C7/1093 ,  G11C7/22

Abstract: A method and system for cycle accurate data transfer between skewed source synchronous clocks is envisaged. The procedure starts through reset. On reset, both the write and read address registers are set to point to location 0. Source clock is stopped to disable active clock edges to both write and read address registers during the reset procedure. The source clock is subsequently started to deliver active edges to both write and read address registers. On every active source clock edge, data is pushed into the data register based on the location pointed by write address register. On every skewed active clock edge, data is read from the data register based on the address pointed by read address register. Due to the delayed nature of clock reaching the read address register, write address register increments first and stores data into the data register.

Abstract translation: 设想了偏斜源同步时钟之间的循环精确数据传输的方法和系统。 程序从复位开始。 复位时，写入和读取地址寄存器均设置为指向位置0.源时钟停止，以在复位过程中禁用写入和读取地址寄存器的有效时钟边沿。 源时钟随后开始向写入和读取地址寄存器传送有效边沿。 在每个有源源时钟沿，数据按写地址寄存器指向的位置被推入数据寄存器。 在每个偏置的有源时钟沿，根据读地址寄存器指向的地址从数据寄存器读取数据。 由于时钟到达读地址寄存器的延迟性，写地址寄存器首先增加，并将数据存储到数据寄存器中。

公开(公告)号：WO2016203491A3

公开(公告)日：2016-12-22

申请号：PCT/IN2016/000154

申请日：2016-06-14

Applicant: GYAN, Prakash ,  NIDHIR, Kumar

Inventor： GYAN, Prakash ,  NIDHIR, Kumar

IPC: H03K19/00 ,  H03L7/00

Abstract: The present disclosure envisages an asynchronous clock gating circuitry and a method for designing the asynchronous clock gating circuitry. The asynchronous clock gating circuitry could be placed at the very beginning of the clock network, given its design and implementation logic. The asynchronous clock gating circuitry helps meet the timing requirement on the enable pin thereof. The asynchronous clock gating circuitry avoids cumbersome replication of clock gating circuitry during physical implementation of the (circuit) design, and further helps reduce the power consumption levels in sequential circuits.

公开(公告)号：WO2016203490A2

公开(公告)日：2016-12-22

申请号：PCT/IN2016/000152

申请日：2016-06-13

Applicant: GYAN, Prakash ,  NIDHIR, Kumar ,  CHANDRASHEKAR, Narla

Inventor： GYAN, Prakash ,  NIDHIR, Kumar ,  CHANDRASHEKAR, Narla

IPC: G11C11/00

CPC classification number: G11C29/028 ,  G11C11/401 ,  G11C29/023 ,  G11C29/50012

Abstract: A method for automatic calibration of read latency of a memory module is envisaged. The read latency is initially set to a default maximum value. The default maximum value is equivalent to the number of clock cycles required to complete a data read operation. A data pattern to be read from the memory module in consideration of the default maximum value is identified. A memory read operation is preformed, and a first data pattern is captured, in accordance with the default maximum value. The identified data pattern is compared with the first data pattern, and the default maximum value is iteratively calibrated based on the comparison thereof. Aforementioned steps are repeated across a plurality of memory read operations, and variations in the maximum default value are tracked, and an average maximum value is calculated based thereupon. The average maximum value is assigned as the read latency for the memory module.

Abstract translation: 设想了一种用于自动校准存储器模块的读等待时间的方法。 读延迟最初设置为默认最大值。 默认最大值等于完成数据读取操作所需的时钟周期数。 鉴于考虑到默认最大值从存储器模块读取的数据模式。 执行存储器读取操作，并且根据默认最大值捕获第一数据模式。 将识别的数据模式与第一数据模式进行比较，并且基于其比较来迭代地校准默认最大值。 在多个存储器读取操作中重复上述步骤，并且跟踪最大默认值的变化，并且基于此计算平均最大值。 平均最大值被分配为内存模块的读取延迟。