Invention Application
- Patent Title: COMPACT VIA STRUCTURES AND METHOD OF MAKING SAME
- Patent Title (中): 紧凑的结构和制作方法
-
Application No.: PCT/US2016/033812Application Date: 2016-05-23
-
Publication No.: WO2016209462A1Publication Date: 2016-12-29
- Inventor: XIAO, Kai , ENRIQUEZ SHIBAYAMA, Raul , OUYANG, Gong , GUILLEN GONZALEZ, Jose Diego , LEE, Beom-Taek
- Applicant: INTEL CORPORATION
- Applicant Address: 2200 Mission College Boulevard Santa Clara, CA 95054 US
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: 2200 Mission College Boulevard Santa Clara, CA 95054 US
- Agency: MALLIE, Michael, J. et al.
- Priority: US14/752,642 20150626
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K3/40 ; H05K3/42
Abstract:
Techniques and mechanisms to provide a compact arrangement of vias extending through at least a portion of a printed circuit board (PCB) or other substrate. In an embodiment, the substrate includes a dielectric material and a sidewall structure forming a hole region that extends at least partially through the dielectric material. The hole region adjoins each of a first via and a second via, and is also located between the first via and second via. In another embodiment, the first via is coupled to exchange a first signal of a differential signal pair, and the second via is coupled to exchange a second signal of the same differential signal pair.
Information query