Invention Application
- Patent Title: ELECTRONIC PACKAGE AND METHOD FORMING AN ELECTRICAL PACKAGE
- Patent Title (中): 电子封装和形成电子封装的方法
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Application No.: PCT/US2016/043397Application Date: 2016-07-21
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Publication No.: WO2017039866A1Publication Date: 2017-03-09
- Inventor: DARMAWIKARTA, Kristof , SOBIESKI, Daniel , LEE, Kyu Oh , BOYAPATI, Sri Ranga Sai
- Applicant: INTEL CORPORATION
- Applicant Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Agency: PERDOK, Monique M. et al.
- Priority: US14/840,979 20150831
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/532
Abstract:
Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.
Information query
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