公开(公告)号：WO2018125166A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/069321

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： JAIN, Rahul ,  LEE, Kyu Oh ,  ALUR, Siddharth K. ,  JEN, Wei-Lun K. ,  MEHTA, Vipul V. ,  DHALL, Ashish ,  CHAVALI, Sri Chaitra J. ,  MANEPALLI, Rahul N. ,  ALUR, Amruthavalli P. ,  VADLAMANI, Sai

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L23/525 ,  H01L23/538 ,  H01L23/12 ,  H01L23/00 ,  H01L25/065

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：WO2016137452A1

公开(公告)日：2016-09-01

申请号：PCT/US2015/017435

申请日：2015-02-25

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  LEE, Kyu Oh

IPC: H01L23/48 ,  H01L25/065

CPC classification number: H01L24/05 ,  B23K35/262 ,  C22C13/00 ,  C22C19/03 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05564 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/0568 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81444 ,  H01L2924/01015 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.

Abstract translation: 表面光洁度可以形成在微电子结构中，其中表面光洁度可以包括多层夹层结构。 因此，可以通过不同的材料层来满足层间结构的所需特性，例如顺应性和耐电迁移性，而是试图用单层实现这些特性。 在一个实施例中，多层夹层结构可以包括双层结构，其中第一层在焊料互连附近形成，并且包括与焊料互连形成韧性接头的材料，以及包括具有强电化学材料的第二层 - 在第一层和互连衬垫之间形成的迁移电阻。 在另一实施例中，第三层可以形成在互连焊盘附近，该互连焊盘包括与互连焊盘形成延性接头的材料。

公开(公告)号：WO2019221843A1

公开(公告)日：2019-11-21

申请号：PCT/US2019/026621

申请日：2019-04-09

Applicant: INTEL CORPORATION

Inventor： LEE, Kyu Oh ,  VADLAMANI, Sai ,  JAIN, Rahul ,  ZHAO, Junnan ,  PARK, Ji Yong ,  XU, Cheng ,  KIM, Seo Young

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L23/525

Abstract: Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure.

公开(公告)号：WO2019066832A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/053859

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： ZHAO, Junnan ,  WANG, Ying ,  XU, Cheng ,  LEE, Kyu Oh ,  LI, Sheng ,  DENG, Yikang

IPC: H01F27/00 ,  H01F41/00

Abstract: Described herein are magnetic core inductors (MCI) and methods for manufacturing magnetic core inductors. A first embodiment of the MCI can be a snake-configuration MCI. The snake-configuration MCI can be formed by creating an opening in a base material, such as copper, and providing a nonconductive magnetic material in the opening. The inductor can be further formed by forming plated through holes into the core material. The conductive elements for the inductor can be formed in the plated through holes. The nonconductive magnetic material surrounds each conductive element and plated through hole. In embodiments, a layered coil inductor can be formed by drilling a laminate to form a cavity through the laminate within the metal rings of the layered coil inductor. The nonconductive magnetic material can be provided in the cavity.

公开(公告)号：WO2018182652A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/025199

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： VADLAMANI, Sai ,  ALEKSOV, Aleksandar ,  JAIN, Rahul ,  LEE, Kyu Oh ,  DARMAWIKARTA, Kristof Kuwawi ,  MAY, Robert Alan ,  BOYAPATI, Sri Ranga Sai ,  KAMGAING, Telesphor

IPC: H01L23/00 ,  H01L23/522

Abstract: Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.

公开(公告)号：WO2018052600A1

公开(公告)日：2018-03-22

申请号：PCT/US2017/046745

申请日：2017-08-14

Applicant: INTEL CORPORATION

Inventor： JAIN, Rahul ,  LEE, Kyu Oh ,  SCHUCKMAN, Amanda E. ,  CHO, Steve S.

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/485

Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.

Abstract translation: 在集成电路封装衬底上提供与表面水平微凸块有效连接的技术和机制。 在一个实施例中，不同的金属被不同地电镀以形成延伸穿过衬底的表面级电介质到包括铜的种子层的微凸块。 微凸块包括镍和锡，其中镍有助于缓解晶种层铜的吸收。 在另一个实施例中，微凸块具有沿着微凸块的高度在不同区域中不同的锡质量分数或镍质量分数。

公开(公告)号：WO2017039866A1

公开(公告)日：2017-03-09

申请号：PCT/US2016/043397

申请日：2016-07-21

Applicant: INTEL CORPORATION

Inventor： DARMAWIKARTA, Kristof ,  SOBIESKI, Daniel ,  LEE, Kyu Oh ,  BOYAPATI, Sri Ranga Sai

IPC: H01L23/00 ,  H01L23/532

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/113 ,  H05K3/0041 ,  H05K3/181 ,  H05K3/188 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09218 ,  H05K2201/09372 ,  H05K2201/095 ,  H05K2201/096 ,  H05K2201/09654 ,  H05K2203/0548

Abstract: Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.

Abstract translation: 一些示例形式涉及电子包装。 电子封装包括第一电介质层，其包括形成在第一电介质层的表面上的电迹线和在第一电介质层的表面上的第二电介质层。 第二电介质层包括开口。 电迹线在开口内。 电子封装包括电互连，其填充开口并且在第二电介质层的上表面上方延伸，使得电互连电连接到第一电介质层上的电迹线。

公开(公告)号：WO2016160189A1

公开(公告)日：2016-10-06

申请号：PCT/US2016/019574

申请日：2016-02-25

Applicant: INTEL CORPORATION

Inventor： LEE, Kyu Oh ,  ZHOU, Zheng ,  SALAMA, Islam A. ,  EID, Feras ,  OSTER, Sasha N. ,  KONG, Lay Wai ,  SOTO GONZALEZ, Javier

IPC: B81B7/02

CPC classification number: B81B7/0077 ,  B81C2203/0109

Abstract: Methods of forming sensor integrated package devices and structures formed thereby are described. An embodiment includes providing a substrate core, wherein a first conductive trace structure and a second conductive trace structure are disposed on the substrate core, forming a cavity between the first conductive trace structure and the second conductive trace structure, and placing a magnet on a resist material disposed on a portion of each of the first and second conductive trace structures, wherein the resist material does not extend over the cavity.

Abstract translation: 描述形成传感器集成封装器件和由此形成的结构的方法。 一个实施例包括提供衬底芯，其中第一导电迹线结构和第二导电迹线结构设置在衬底芯上，在第一导电迹线结构和第二导电迹线结构之间形成空腔，并将磁体放置在抗蚀剂上 设置在第一和第二导电迹线结构中的每一个的一部分上的材料，其中抗蚀剂材料不在空腔上延伸。

公开(公告)号：WO2012087556A2

公开(公告)日：2012-06-28

申请号：PCT/US2011/063409

申请日：2011-12-06

Applicant: INTEL CORPORATION ,  HLAD, Mark S. ,  SALAMA, Islam A. ,  ROY, Mihir K. ,  WU, Tao ,  LIU, Yueli ,  LEE, Kyu Oh

Inventor： HLAD, Mark S. ,  SALAMA, Islam A. ,  ROY, Mihir K. ,  WU, Tao ,  LIU, Yueli ,  LEE, Kyu Oh

IPC: H01L21/60 ,  H01L23/48

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Abstract translation: 封装基板实现减小的凸点间距及其封装组件。 表面层金属特征被嵌入在表面层级介质层中，表面层从表面层级介质的顶表面突出，用于在没有阻焊层的情况下组装到具有焊接连接点的IC芯片上。 封装基板的制作能够实现多层次的走线布线，每条走线布线层次都能够减小最小走线宽度和间距。

公开(公告)号：WO2020005559A1

公开(公告)日：2020-01-02

申请号：PCT/US2019/037021

申请日：2019-06-13

Applicant: INTEL CORPORATION

Inventor： XU, Cheng ,  JAIN, Rahul ,  KIM, Seo Young ,  LEE, Kyu Oh ,  PARK, Ji Yong ,  VADLAMANI, Sai ,  ZHAO, Junnan

IPC: H01G4/33 ,  H01G4/30

Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.