Invention Application
WO2017052899A1 GLITCH-FREE BANDWIDTH-SWITCHING SCHEME FOR AN ANALOG PHASE-LOCKED LOOP (PLL) 审中-公开
用于模拟锁相环(PLL)的无刷宽带切换方案

  • Patent Title: GLITCH-FREE BANDWIDTH-SWITCHING SCHEME FOR AN ANALOG PHASE-LOCKED LOOP (PLL)
  • Patent Title (中): 用于模拟锁相环(PLL)的无刷宽带切换方案
  • Application No.: PCT/US2016/048214
    Application Date: 2016-08-23
  • Publication No.: WO2017052899A1
    Publication Date: 2017-03-30
  • Inventor: ZHUANG, JingchengPARK, Jong MinLEUNG, Lai KanTANG, Yiwu
  • Applicant: QUALCOMM INCORPORATED
  • Applicant Address: ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714 US
  • Assignee: QUALCOMM INCORPORATED
  • Current Assignee: QUALCOMM INCORPORATED
  • Current Assignee Address: ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714 US
  • Agency: READ, Randol W. et al.
  • Priority: US62/233,073 20150925; US15/060,198 20160303
  • Main IPC: H03L7/107
  • IPC: H03L7/107
GLITCH-FREE BANDWIDTH-SWITCHING SCHEME FOR AN ANALOG PHASE-LOCKED LOOP (PLL)
Abstract:
Certain aspects of the present disclosure provide techniques and apparatus for glitch-free bandwidth switching in a phase-locked loop (PLL). One example PLL generally includes a voltage-controlled oscillator (VCO) comprising a first variable capacitive element and a second variable capacitive element and a bandwidth adjustment circuit comprising a first switch in parallel with a resistor of a resistor-capacitor (RC) network. The bandwidth adjustment circuit is configured to open the first switch for a first bandwidth mode, close the first switch in a transition from the first bandwidth mode to a second bandwidth mode, and control a capacitance of the second variable capacitive element based on a voltage of a node of the RC network.
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