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    GLITCH-FREE BANDWIDTH-SWITCHING SCHEME FOR AN ANALOG PHASE-LOCKED LOOP (PLL)
    2.
    发明申请
    GLITCH-FREE BANDWIDTH-SWITCHING SCHEME FOR AN ANALOG PHASE-LOCKED LOOP (PLL) 审中-公开
    用于模拟锁相环（PLL）的无刷宽带切换方案

    公开(公告)号：WO2017052899A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2016/048214

    申请日：2016-08-23

    Applicant: QUALCOMM INCORPORATED

    Inventor： ZHUANG, Jingcheng ,  PARK, Jong Min ,  LEUNG, Lai Kan ,  TANG, Yiwu

    IPC: H03L7/107

    CPC classification number: H03L7/093 ,  H03L7/099 ,  H03L7/1072 ,  H03L7/1075

    Abstract: Certain aspects of the present disclosure provide techniques and apparatus for glitch-free bandwidth switching in a phase-locked loop (PLL). One example PLL generally includes a voltage-controlled oscillator (VCO) comprising a first variable capacitive element and a second variable capacitive element and a bandwidth adjustment circuit comprising a first switch in parallel with a resistor of a resistor-capacitor (RC) network. The bandwidth adjustment circuit is configured to open the first switch for a first bandwidth mode, close the first switch in a transition from the first bandwidth mode to a second bandwidth mode, and control a capacitance of the second variable capacitive element based on a voltage of a node of the RC network.

    Abstract translation: 本公开的某些方面提供了在锁相环（PLL）中无毛刺带宽切换的技术和装置。 一个示例PLL通常包括包括第一可变电容元件和第二可变电容元件的压控振荡器（VCO），以及包括与电阻器 - 电容器（RC）网络的电阻器并联的第一开关的带宽调整电路。 带宽调整电路被配置为在第一带宽模式下打开第一开关，在从第一带宽模式到第二带宽模式的转变中关闭第一开关，并且基于第一可变电容元件的电压来控制第二可变电容元件的电容 RC网络的一个节点。

    SYSTEMS AND METHODS FOR FREQUENCY DETECTION
    3.
    发明申请
    SYSTEMS AND METHODS FOR FREQUENCY DETECTION 审中-公开
    用于频率检测的系统和方法

    公开(公告)号：WO2015134189A1

    公开(公告)日：2015-09-11

    申请号：PCT/US2015/016405

    申请日：2015-02-18

    Applicant: QUALCOMM INCORPORATED

    Inventor： MURPHY, Glenn ,  ZHUANG, Jingcheng ,  KONG, Xiaohua ,  LADD, William Knox

    IPC: H04L25/02 ,  H04L25/49

    CPC classification number: H04L25/0262 ,  H04L25/4902

    Abstract: Methods and systems according to one or more embodiments are provided for frequency detection. In an embodiment, a frequency detector is provided that includes a capacitor that discharges or charges responsive to binary states of an input signal.

    Abstract translation: 提供根据一个或多个实施例的方法和系统用于频率检测。 在一个实施例中，提供了一种频率检测器，其包括响应于输入信号的二进制状态而放电或充电的电容器。

    METHODS AND APPARATUS FOR A TRANSMIT PATH WITH FREQUENCY HOPPING PHASE LOCKED LOOP
    4.
    发明申请
    METHODS AND APPARATUS FOR A TRANSMIT PATH WITH FREQUENCY HOPPING PHASE LOCKED LOOP 审中-公开
    用于具有频率相位锁定环路的发射路径的方法和装置

    公开(公告)号：WO2017052956A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2016/048581

    申请日：2016-08-25

    Applicant: QUALCOMM INCORPORATED

    Inventor： ASURI, Bhushan Shanti ,  ZHUANG, Jingcheng ,  SAMPATH, Praveen ,  PATEL, Shrenik ,  DUNWORTH, Jeremy Darren ,  LEUNG, Lai Kan ,  SAHOTA, Gurkanwal Singh ,  PARK, Jong Min

    IPC: H04B1/7136

    CPC classification number: H04W72/04 ,  H04B1/713 ,  H04B1/7136 ,  H04B2001/71362 ,  H04L5/0044 ,  H04L5/0053 ,  H04L5/0094

    Abstract: An apparatus comprising a transmit path, a plurality of local oscillators and a control unit.The control unit may be configured to: receive an upcoming resource block (RB) allocation; determine whether the upcoming RB allocation is the same as the current RB allocation; in response to determining that the upcoming RB allocation is different than the current RB allocation: select an unused LO of the plurality of LOs; determine whether a number of allocated RBs associated with the upcoming RB allocation is greater than a threshold; and in response to determining that the number of allocated RBs associated with the upcoming RB allocation is not greater than the threshold, tune the selected LO to a frequency corresponding to the upcoming RB allocation.

    Abstract translation: 一种装置，包括发送路径，多个本地振荡器和控制单元。控制单元可以被配置为：接收即将到来的资源块（RB）分配; 确定即将到来的RB分配是否与当前的RB分配相同; 响应于确定即将到来的RB分配不同于当前RB分配：选择多个LO中的未使用的LO; 确定与即将到来的RB分配相关联的分配的RB的数量是否大于阈值; 并且响应于确定与即将到来的RB分配相关联的分配的RB的数量不大于阈值，将所选择的LO调谐到对应于即将到来的RB分配的频率。

    RESETTABLE VOLTAGE CONTROLLED OSCILLATORS (VCOs) FOR CLOCK AND DATA RECOVERY (CDR) CIRCUITS, AND RELATED SYSTEMS AND METHODS
    6.
    发明申请
    RESETTABLE VOLTAGE CONTROLLED OSCILLATORS (VCOs) FOR CLOCK AND DATA RECOVERY (CDR) CIRCUITS, AND RELATED SYSTEMS AND METHODS 审中-公开
    用于时钟和数据恢复（CDR）电路的可复位电压控制振荡器（VCO）及相关系统和方法

    公开(公告)号：WO2013123427A1

    公开(公告)日：2013-08-22

    申请号：PCT/US2013/026488

    申请日：2013-02-15

    Applicant: QUALCOMM INCORPORATED

    Inventor： ZHUANG, Jingcheng ,  DANG, Nam V.

    IPC: H04L7/033 ,  H03L7/099 ,  H03K3/03

    CPC classification number: H04L25/02 ,  H03K3/0322 ,  H03L7/0995 ,  H03L2207/06 ,  H04L7/033

    Abstract: Clock and data recovery (CDR) circuits and resettable voltage controlled oscillators (VCOs) are disclosed. In one embodiment, the CDR circuit includes a sampler configured to receive a data stream in a data path and sample the data stream. However, a clock signal of the data stream needs to be recovered to sample the data stream since the data stream may not be accompanied by the clock signal. To recover the clock signal from the data stream, the CDR circuit may have a resettable VCO configured to generate a clock output. The sampler and the resettable VCO may be operably associated so that the sampler samples the data stream in the data path based on the clock output. The resettable VCO can be reset to adjust a clock phase of the clock output and help reduce sampling errors resulting from drift of the clock output and/or the data stream.

    Abstract translation: 公开了时钟和数据恢复（CDR）电路和可复位的压控振荡器（VCO）。 在一个实施例中，CDR电路包括被配置为在数据路径中接收数据流并对数据流进行采样的采样器。 然而，需要恢复数据流的时钟信号以采样数据流，因为数据流可能不伴随时钟信号。 为了从数据流恢复时钟信号，CDR电路可以具有被配置为产生时钟输出的可复位VCO。 采样器和可复位VCO可以可操作地相关联，使得采样器基于时钟输出对数据路径中的数据流进行采样。 可复位的VCO可以复位以调整时钟输出的时钟相位，并有助于减少由于时钟输出和/或数据流的漂移而导致的采样错误。

    PHASE FREQUENCY DETECTOR LINEARIZATION USING SWITCHING SUPPLY
    7.
    发明申请
    PHASE FREQUENCY DETECTOR LINEARIZATION USING SWITCHING SUPPLY 审中-公开

    公开(公告)号：WO2018231366A1

    公开(公告)日：2018-12-20

    申请号：PCT/US2018/031412

    申请日：2018-05-07

    Applicant: QUALCOMM INCORPORATED

    Inventor： ZHUANG, Jingcheng

    IPC: H03L7/089

    Abstract: A phase frequency detector (PFD) isolates supply (e.g., voltage supply) to a reference path and a feedback path of a phase locked loop (PLL) such that the power supply to the reference path is independent of the power supply to the feedback path. This isolation improves linearity. In one instance, the PFD includes a supply voltage, one or more switches, a reference capacitor and a feedback capacitor. The reference capacitor is selectively coupled to the supply voltage via the one or more switches and the feedback capacitor is selectively coupled to the supply voltage via the one or more switches.

    TIME-TO-DIGITAL CONVERSION WITH LATCH-BASED RING
    8.
    发明申请
    TIME-TO-DIGITAL CONVERSION WITH LATCH-BASED RING 审中-公开

    公开(公告)号：WO2018102068A2

    公开(公告)日：2018-06-07

    申请号：PCT/US2017/059734

    申请日：2017-11-02

    Applicant: QUALCOMM INCORPORATED

    Inventor： ZHUANG, Jingcheng

    IPC: G04F10/00

    Abstract: An integrated circuit (IC) is disclosed for time-to-digital conversion with a latch-based ring. In example aspects, the IC includes a ring, a counter, an encoder, and time-to-digital converter (TDC) control circuitry. The ring includes multiple ring stages and propagates a ring signal between successive ring stages. Each respective ring stage includes latch circuitry to secure a state of the ring signal at the respective ring stage. The ring provides a ring output signal using the latch circuitry of each of the ring stages. The ring is coupled to the counter. The counter increments a counter value responsive to the ring signal and provides a counter output signal based on the counter value. The encoder is coupled to the ring and the counter. The encoder generates a TDC output signal based on the ring and counter output signals. The TDC control circuitry operates the ring responsive to a TDC input signal.

    RE-TIMING BASED CLOCK GENERATION AND RESIDUAL SIDEBAND (RSB) ENHANCEMENT CIRCUIT
    9.
    发明申请
    RE-TIMING BASED CLOCK GENERATION AND RESIDUAL SIDEBAND (RSB) ENHANCEMENT CIRCUIT 审中-公开
    基于重新计时的时钟生成和剩余边带（RSB）增强电路

    公开(公告)号：WO2018052982A3

    公开(公告)日：2018-03-22

    申请号：PCT/US2017/051336

    申请日：2017-09-13

    Applicant: QUALCOMM INCORPORATED

    Inventor： PAUL, Animesh ,  ZHUANG, Jingcheng ,  CHEN, Xinhua ,  SRIDHARA, Ravi

    IPC: H03K5/156 ,  H03K21/02

    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor (402) connected in cascode with a second transistor (404), wherein an input clock (Clk_in) node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit (406) having an input coupled to the input clock node, wherein an output (Div_out) of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node (Clk_out) of the circuit is coupled to drains of the first and second transistors.

    Abstract translation: 本公开的某些方面一般涉及用于生成时钟信号的方法和装置。 例如，本公开的某些方面提供了一种时钟生成电路。 时钟生成电路可以包括与第二晶体管（404）共源共栅连接的第一晶体管（402），其中电路的输入时钟（Clk_in）节点耦合到第一和第二晶体管的栅极。 时钟生成电路还可以包括分频器电路（406），该分频器电路具有耦合到输入时钟节点的输入，其中分频器电路的输出（Div_out）被耦合到第二晶体管的源极，并且其中输出节点 （Clk_out）耦合到第一和第二晶体管的漏极。

    DUAL MODE CLOCK/DATA RECOVERY CIRCUIT
    10.
    发明申请
    DUAL MODE CLOCK/DATA RECOVERY CIRCUIT 审中-公开
    双模式时钟/数据恢复电路

    公开(公告)号：WO2013112763A1

    公开(公告)日：2013-08-01

    申请号：PCT/US2013/023025

    申请日：2013-01-24

    Applicant: QUALCOMM INCORPORATED

    Inventor： ZHUANG, Jingcheng ,  DANG, Nam, V. ,  KONG, Xiaohua ,  ZHU, Zhi ,  SOWLATI, Tirdad ,  AMELIFARD, Behnam

    IPC: H03L7/08 ,  H03L7/087 ,  H03L7/091 ,  H03L7/14 ,  H04L7/033

    CPC classification number: H03L7/0807 ,  H03L7/087 ,  H03L7/091 ,  H03L7/14 ,  H04L7/0004 ,  H04L7/033

    Abstract: A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.

    Abstract translation: 时钟/数据恢复电路包括边沿检测器电路，其可操作以接收串行数据脉冲串并且响应于串行数据脉冲串的第一个边沿而产生复位信号。 时钟/数据恢复电路还可以包括耦合到边缘检测器电路的振荡器。 振荡器在接收到串行数据脉冲串之前锁定到目标数据速率，并响应于复位信号锁定到串行数据脉冲串的相位上。 时钟/数据恢复电路还可以包括接收串行数据突发的相位检测器电路。 相位检测器电路耦合到振荡器。 相位检测器电路调节振荡器以在串行数据突发期间将锁定保持在串行数据突发的相位上。

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