Invention Application
WO2017172251A1 METHOD AND APPARATUS FOR PROCESSING SEQUENTIAL WRITES TO PORTIONS OF AN ADDRESSIBLE UNIT
审中-公开
处理顺序写入可寻址单元部分的方法和装置
- Patent Title: METHOD AND APPARATUS FOR PROCESSING SEQUENTIAL WRITES TO PORTIONS OF AN ADDRESSIBLE UNIT
- Patent Title (中): 处理顺序写入可寻址单元部分的方法和装置
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Application No.: PCT/US2017/020538Application Date: 2017-03-02
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Publication No.: WO2017172251A1Publication Date: 2017-10-05
- Inventor: HADY, Frank T.
- Applicant: INTEL CORPORATION
- Applicant Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Agency: VICTOR, David W.
- Priority: US15/089,333 20160401
- Main IPC: G06F12/02
- IPC: G06F12/02
Abstract:
Provided are an apparatus and method for processing sequential writes portions of an addressable unit memory dies to store data. A write to a first portion of an addressable unit is received and the write is written to the first portion of the addressable unit. A next write is received to a next portion of the addressable unit following a previous write to a previous portion of the addressable unit. The next write is written to the next portion of the addressable unit sequentially following the previous portion in response to the next write being sequential with respect to the previous write. Data other than the next write is written to the addressable unit following the previous portion in response to the next write not being sequential with respect to the previous write.
Information query
