公开(公告)号：WO2017172251A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/020538

申请日：2017-03-02

Applicant: INTEL CORPORATION

Inventor： HADY, Frank T.

IPC: G06F12/02

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0679 ,  G06F13/16

Abstract: Provided are an apparatus and method for processing sequential writes portions of an addressable unit memory dies to store data. A write to a first portion of an addressable unit is received and the write is written to the first portion of the addressable unit. A next write is received to a next portion of the addressable unit following a previous write to a previous portion of the addressable unit. The next write is written to the next portion of the addressable unit sequentially following the previous portion in response to the next write being sequential with respect to the previous write. Data other than the next write is written to the addressable unit following the previous portion in response to the next write not being sequential with respect to the previous write.

Abstract translation: 提供了用于处理可寻址单元存储器裸片的顺序写入部分以存储数据的装置和方法。 接收对可寻址单元的第一部分的写入并将写入写入可寻址单元的第一部分。 在先前写入可寻址单元的先前部分之后，接下来的写入被接收到可寻址单元的下一部分。 下一次写入被写入到可寻址单元的下一部分，其顺序在前一部分之后，以响应下一次写入相对于先前写入的顺序。 下一次写入之后的数据被写入到前一部分之后的可寻址单元，以响应下一次写入不相对于前一次写入而连续。

公开(公告)号：WO2017172248A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/020532

申请日：2017-03-02

Applicant: INTEL CORPORATION

Inventor： HADY, Frank T.

IPC: G06F12/02

Abstract: Provided are an apparatus and method for processing sequential writes to a block group of physical blocks in a memory device. Sequential write data for a plurality of consecutive logical addresses is received and a determination is made of consecutive physical blocks comprising a block group. Each of the physical blocks has data for a plurality of the consecutive logical addresses. The sequential write data is written to consecutive physical data locations having data for the determined consecutive physical blocks of the block group. The block group metadata for the block group is updated.

Abstract translation: 提供了用于处理对存储器件中的物理块的块组的顺序写入的装置和方法。 接收多个连续逻辑地址的顺序写入数据并且确定包括块组的连续物理块。 每个物理块具有用于多个连续逻辑地址的数据。 顺序写入数据被写入到具有用于块组的确定的连续物理块的数据的连续物理数据位置。 块组的块组元数据更新。

公开(公告)号：WO2013101050A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067824

申请日：2011-12-29

Applicant: INTEL CORPORATION ,  FANNING, Blaise ,  QAWAMI, Shekoufeh ,  TETRICK, Raymond S. ,  HADY, Frank T.

Inventor： FANNING, Blaise ,  QAWAMI, Shekoufeh ,  TETRICK, Raymond S. ,  HADY, Frank T.

IPC: G06F12/00 ,  G11C13/02 ,  G11C16/00

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/2024 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7204 ,  G11C7/1006 ,  G11C11/56 ,  G11C16/00 ,  Y02D10/13

Abstract: Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system.

Abstract translation: 公开了用于实现具有直接访问的多级存储器的方法，设备和系统的实施例。 在一个实施例中，该方法包括指定要用作动态随机存取存储器（DRAM）的存储器备选方案的计算机系统中的非易失性随机存取存储器（NVRAM）的量。 该方法通过指定要用作大容量存储设备的存储备用的第二数量的NVRAM来继续。 然后，该方法在计算机系统的操作期间将存储器备选指定中的第一数量的NVRAM的至少第一部分重新指定为存储备选指定。 最后，该方法在计算机系统的操作期间将第二数量的NVRAM的至少第一部分从存储替代指定重新指定到存储器备选指定。

公开(公告)号：WO2013058730A1

公开(公告)日：2013-04-25

申请号：PCT/US2011/056581

申请日：2011-10-17

Applicant: INTEL CORPORATION ,  MOONEY, Stephen R. ,  HECK, Howard L ,  JAUSSI, James E. ,  HADY, Frank T. ,  CASPER, Bryan K.

Inventor： MOONEY, Stephen R. ,  HECK, Howard L ,  JAUSSI, James E. ,  HADY, Frank T. ,  CASPER, Bryan K.

IPC: G06F13/14 ,  G06F1/00

CPC classification number: G06F13/385 ,  G06F1/266 ,  H01H9/54 ,  H01R13/6658 ,  Y10T307/74

Abstract: Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a first set of contacts, a second set of contacts connected to the one or more signaling circuits, and logic to receive a configuration command. The logic may also connect the first set of contacts to the voltage regulator if the configuration command corresponds to a first protocol. If the configuration command corresponds to a second protocol, on the other hand, the logic can connect the first set of contacts to the one or more signaling circuits.

Abstract translation: 互连设备的系统和方法可以包括具有电压调节器，一个或多个信令电路，第一组触点，连接到一个或多个信号电路的第二组触点和逻辑电路的输入/输出（IO）连接器组件 接收配置命令。 如果配置命令对应于第一协议，逻辑还可以将第一组触点连接到电压调节器。 如果配置命令对应于第二协议，另一方面，逻辑可以将第一组联系人连接到一个或多个信令电路。

公开(公告)号：WO2013058729A1

公开(公告)日：2013-04-25

申请号：PCT/US2011/056574

申请日：2011-10-17

Applicant: INTEL CORPORATION ,  JAUSSI, James E. ,  MOONEY, Stephen R. ,  HECK, Howard L ,  CASPER, Bryan K. ,  HADY, Frank T.

Inventor： JAUSSI, James E. ,  MOONEY, Stephen R. ,  HECK, Howard L ,  CASPER, Bryan K. ,  HADY, Frank T.

IPC: G06F13/14 ,  G06F1/26

CPC classification number: G06F1/26 ,  G06F1/266 ,  G06F1/3203

Abstract: Systems and methods of interconnecting devices may include an input/output (IO) connector having a buffer with an integrated voltage regulator. The integrated voltage regulator may include a first supply output and a second supply output, wherein the IO connector includes an IO power contact coupled to the first supply output. The IO connector may also include a logic power contact coupled to the second supply output. In one example, a host device may issue power management commands to the buffer in order to scale the second supply output independently of the first supply output.

Abstract translation: 互连设备的系统和方法可以包括具有集成稳压器的缓冲器的输入/输出（IO）连接器。 集成电压调节器可以包括第一电源输出和第二电源输出，其中IO连接器包括耦合到第一电源输出的IO电源触点。 IO连接器还可以包括耦合到第二电源输出的逻辑电源触点。 在一个示例中，主机设备可以向缓冲器发布功率管理命令，以便与第一电源输出独立地缩放第二电源输出。