An etched planarized VCSEL includes: an active region (122) comprising MQW (138,140); a blocking region (127,160) over the active region which may be made form InGaP, and defining apertures therein; and conductive channel cores (129,162) in the apertures which may be made from AIGaAs, wherein the conductive channel cores and blocking region form an isolation region (128). The VCSEL may comprise spacer layers (148,150). A method of making the VCSEL includes: forming the active region; forming the blocking region over the active region; etching the apertures in the blocking region; and forming the conductive channel cores in the apertures of the blocking region. Another etched planarized VCSEL includes: an active region; a conductive region over the active region, and defining apertures therein; and blocking cores in the apertures, wherein the blocking cores and conductive region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the conductive region over the active region; etching the apertures in the conductive region; and forming the blocking cores in the apertures of the conductive region. This kind of providing a current aperture for a VCSEL avoids the reliability problems of current apertures provided by lateral oxidisation of a layer in the mesa of the VCSEL.