公开(公告)号：WO2020081713A1

公开(公告)日：2020-04-23

申请号：PCT/US2019/056575

申请日：2019-10-16

申请人： FINISAR CORPORATION

发明人： DING, Frank Lei ,  AMIRKIAI, Maziar ,  MU, Jianwei ,  DENG, Hongyu ,  WU, Tao

IPC分类号： G02B6/42 ,  H05K1/18 ,  H05K7/20 ,  H05K9/00

摘要： A resistance weldable cover for an OSA may include multiple walls, one or more supports, and an opening disposed in one of the walls. The walls may define an interior cavity within the walls. The one or more supports may extend from one or more of the walls. Each of the one or more supports may be weldable to a heat sink stiffener. The opening may be sized and shaped to receive at least a portion of a barrel such that optical signals are transmittable between the interior cavity and the barrel.

公开(公告)号：WO2019213163A1

公开(公告)日：2019-11-07

申请号：PCT/US2019/030047

申请日：2019-04-30

申请人： FINISAR CORPORATION

发明人： LANDRY, Gary ,  GRAY, Timo ,  O'DANIEL, Jason

IPC分类号： G02B6/028 ,  G02B6/14 ,  H04B10/2581

摘要： In one example, an optical device may include a waveguide having a core index of refraction that decreases along a length of the waveguide and an edge index of refection of the waveguide that is constant along the length of the waveguide. The central rays of the optical signals travelling through the waveguide may be refracted towards higher radii while the outer rays propagate unaffected. The optical device may decrease dispersion of the optical signals travelling through an optical fiber.

公开(公告)号：WO2019125963A1

公开(公告)日：2019-06-27

申请号：PCT/US2018/065827

申请日：2018-12-14

申请人： FINISAR CORPORATION

发明人： WANG, William H. ,  SHI, Shamei ,  MOORE, Joshua

IPC分类号： G02B6/42 ,  G02B6/38 ,  G02B6/40

CPC分类号： G02B6/43 ,  G02B6/381 ,  G02B6/3825 ,  G02B6/3885 ,  G02B6/3893 ,  G02B6/3897 ,  G02B6/403 ,  G02B6/422 ,  G02B6/4246 ,  G02B6/4256 ,  G02B6/4261 ,  G02B6/4292

摘要： An alignment connector for an optoelectronic module can include: a front end having a first gripper arm and a second gripper arm with an alignment connector aperture between the first gripper arm and the second gripper arm; a base having a bottom surface and a receptacle surface; the back end having a first back wall and a second back wall with a back gap therebetween; and a ferrule receptacle extending to a medial region where the alignment connector aperture extends from, and including a portion of the receptacle surface, the ferrule receptacle being defined by a first side wall having a first latch arm and a second side wall having a second latch arm. The alignment connector can be included in a module with a bail or pull-tab. Alternatively, the first gripper arm and second gripper arm can be mounted directly to a module housing.

公开(公告)号：WO2019094505A1

公开(公告)日：2019-05-16

申请号：PCT/US2018/059679

申请日：2018-11-07

申请人： FINISAR CORPORATION

发明人： WESTBERGH, Petter

IPC分类号： H01S5/183 ,  H01S5/10 ,  H01S5/042 ,  H01S5/20

摘要： A VCSEL may include a bottom DBR mirror and a top DBR mirror above the bottom DBR mirror. The VCSEL may include a vertical optical cavity located within a portion of the bottom and top DBR mirrors. The vertical optical cavity may be configured to emit an optical signal. The VCSEL may include a lateral feedback optical cavity located within a different portion of the bottom and the top DBR mirrors configured to receive a feedback bias signal configured to bias the lateral feedback optical cavity to adjust the optical signal. The VCSEL may include an active region formed between the bottom and the top DBR mirrors that may include an oxide layer defining an oxide aperture. The VCSEL may include an isolation implant configured to electrically isolate the vertical optical cavity from the feedback optical cavity and to create a first and a second aperture within the oxide aperture.

公开(公告)号：WO2019089394A1

公开(公告)日：2019-05-09

申请号：PCT/US2018/057868

申请日：2018-10-26

申请人： FINISAR CORPORATION

发明人： RAY, Sagar

IPC分类号： H04B10/69 ,  H03F3/45

摘要： A circuit and method in an amplifier circuit for filtering a DC offset in differential input signals and inserting a programmable adjustable crosspoint offset in differential output signals. An amplifier circuit includes a differential amplifier circuit configured to amplify differential input signals into differential output signal. The amplifier circuit further includes a feedback circuit coupled between the differential output signals and the differential input signals. The feedback circuit is configured to generate a programmably adjustable crosspoint offset in the differential output signal and a programmably adjustable cutoff frequency of the feedback circuit. An amplifier method includes amplifying differential input signals into differential output signals, generating a programmably adjustable crosspoint offset in the differential output signal, and generating a programmably adjustable cutoff frequency of a feedback circuit between the differential output signals and the differential input signals.

公开(公告)号：WO2018170177A1

公开(公告)日：2018-09-20

申请号：PCT/US2018/022507

申请日：2018-03-14

申请人： FINISAR CORPORATION

发明人： WANG, William, H. ,  SHI, Shamei ,  PENG, Huaping ,  ZHANG, Ranran ,  AN, Haijun

IPC分类号： G02B6/42

摘要： In an embodiment, an optoelectronic module includes a printed circuit board (PCB) and a lens block. The printed circuit board (PCB) includes at least one of an optical transmitting or receiving array. The lens block may be configured for directly coupling light between one of the optical transmitting or receiving array to optical fibers in an optical cable. A method may include directly coupling light between one of an optical transmitting or receiving array and a lens block, and further coupling the light through the lens block directly to an optical fiber of an optical cable externally coupled to the optoelectronic module.

公开(公告)号：WO2018031582A1

公开(公告)日：2018-02-15

申请号：PCT/US2017/045965

申请日：2017-08-08

申请人： FINISAR CORPORATION

发明人： GRAHAM, Luke ,  MACINNES, Andy

IPC分类号： H01S5/183 ,  H01S5/20 ,  H01S5/42

摘要： An etched planarized VCSEL includes: an active region (122) comprising MQW (138,140); a blocking region (127,160) over the active region which may be made form InGaP, and defining apertures therein; and conductive channel cores (129,162) in the apertures which may be made from AIGaAs, wherein the conductive channel cores and blocking region form an isolation region (128). The VCSEL may comprise spacer layers (148,150). A method of making the VCSEL includes: forming the active region; forming the blocking region over the active region; etching the apertures in the blocking region; and forming the conductive channel cores in the apertures of the blocking region. Another etched planarized VCSEL includes: an active region; a conductive region over the active region, and defining apertures therein; and blocking cores in the apertures, wherein the blocking cores and conductive region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the conductive region over the active region; etching the apertures in the conductive region; and forming the blocking cores in the apertures of the conductive region. This kind of providing a current aperture for a VCSEL avoids the reliability problems of current apertures provided by lateral oxidisation of a layer in the mesa of the VCSEL.

摘要翻译： 蚀刻的平面化的VCSEL包括：包括MQW（138,140）的有源区（122） 在可由InGaP制成的有源区上的阻挡区（127,160），并在其中限定孔; 以及可由AlGaAs制成的孔中的导电通道芯（129,162），其中导电通道芯和阻挡区形成隔离区（128）。 VCSEL可以包括间隔层（148,150）。 一种制造VCSEL的方法包括：形成有源区; 在有源区上方形成阻挡区; 蚀刻阻挡区域中的孔; 以及在阻挡区域的孔中形成导电通道芯。 另一种蚀刻平面化VCSEL包括：有源区域; 在有源区上方的导电区域，并在其中限定孔; 并阻挡孔中的芯，其中阻塞芯和导电区形成隔离区。 一种制造VCSEL的方法包括：形成有源区; 在有源区上形成导电区; 蚀刻导电区域中的孔; 以及在导电区域的孔中形成阻塞芯。 这种为VCSEL提供当前孔径避免了由VCSEL台面中的层的横向氧化提供的当前孔径的可靠性问题。

公开(公告)号：WO2017201100A3

公开(公告)日：2017-11-23

申请号：PCT/US2017/032978

申请日：2017-05-16

申请人： FINISAR CORPORATION

发明人： MAHGEREFTEH, Daniel ,  PARK, Bryan

IPC分类号： G02B6/122 ,  G02B6/30

摘要： An optical system includes a silicon (Si) substrate (102), a buried oxide (BOX) layer (104) formed on the substrate (102), a silicon nitride (SiN) layer (112) formed above the BOX layer, and a SiN waveguide (114) formed in the SiN layer (112). In some embodiments, the optical system may additionally include an interposer waveguide (116) adiabatically coupled to the SiN waveguide (114) to form a SiN-interposer adiabatic coupler that includes at least the tapered section of the SiN waveguide, the optical system further including at least one of: a cavity (402) formed in the Si substrate at least beneath the SiN-interposer adiabatic coupler or an oxide overlay (822) formed between a top of a SiN core of the SiN waveguide and a bottom of the interposer waveguide. Alternatively or additionally, the optical system may additionally include a multimode Si-SiN adiabatic coupler that includes a SiN taper (1008) of a SiN waveguide and a Si taper (1006) of a Si waveguide.

公开(公告)号：WO2017201100A2

公开(公告)日：2017-11-23

申请号：PCT/US2017/032978

申请日：2017-05-16

申请人： FINISAR CORPORATION

发明人： MAHGEREFTEH, Daniel ,  PARK, Bryan

IPC分类号： G02B6/122

摘要： An optical system includes a silicon (Si) substrate, a buried oxide (BOX) layer formed on the substrate, a silicon nitride (SiN) layer formed above the BOX layer, and a SiN waveguide formed in the SiN layer. In some embodiments, the optical system may additionally include an interposer waveguide adiabatically coupled to the SiN waveguide to form a SiN-interposer adiabatic coupler that includes at least the tapered section of the SiN waveguide, the optical system further including at least one of: a cavity formed in the Si substrate at least beneath the SiN-interposer adiabatic coupler or an oxide overlay formed between a top of a SiN core of the SiN waveguide and a bottom of the interposer waveguide. Alternatively or additionally, the optical system may additionally include a multimode Si-SiN adiabatic coupler that includes a SiN taper of a SiN waveguide and a Si taper of a Si waveguide.

摘要翻译： 光学系统包括硅（Si）衬底，形成在衬底上的埋入氧化物（BOX）层，形成在BOX层上方的氮化硅（SiN）层以及形成在衬底上的SiN波导 SiN层。 在一些实施例中，光学系统可以另外包括绝缘耦合到SiN波导的中介层波导以形成SiN中介层绝热耦合器，该绝缘耦合器至少包括SiN波导的锥形部分，该光学系统还包括以下中的至少一个： 至少在所述Si衬底下方形成至少在所述SiN-内插器绝热耦合器下方的空腔或者在所述SiN波导的SiN芯的顶部和所述中介层波导的底部之间形成的氧化物覆盖层。 可选地或另外地，光学系统可以另外包括多模Si-SiN绝热耦合器，其包括SiN波导的SiN锥形和Si波导的Si锥形。

公开(公告)号：WO2017185102A1

公开(公告)日：2017-10-26

申请号：PCT/US2017/029216

申请日：2017-04-24

申请人： FINISAR CORPORATION

发明人： CHONG, Kam, Meng ,  SIEW, Chiew, Loon ,  WONG, Yih, Pin ,  SOONG, Chee, Wai ,  ARIFIN, Sarah Idayu Binti, Zainal ,  AZIZI, Aziema Binti, Mohamad ,  SINGH, Shashipal Singh, Dalbir

IPC分类号： B32B7/12 ,  G02B6/42

摘要： In an example, a method may include dispensing a portion of epoxy on a first surface. The method may also include curing the portion of epoxy to form precured epoxy. The method may also include positioning the first surface and a second surface separated from each other by a gap. The precured epoxy is located within the gap between the first surface and the second surface. The method may also include dispensing bulk epoxy into the gap and in contact with the precured epoxy, the first surface, and the second surface. The method may also include curing the bulk epoxy to bond the first surface to the second surface.

摘要翻译： 在一个实例中，一种方法可以包括在第一表面上分配一部分环氧树脂。 该方法还可以包括固化该部分环氧树脂以形成预固化环氧树脂。 该方法还可以包括将第一表面和通过间隙彼此分开的第二表面定位。 预固化环氧树脂位于第一表面和第二表面之间的间隙内。 该方法还可以包括将批量环氧树脂分配到间隙中并且与预固化环氧树脂，第一表面和第二表面接触。 该方法还可以包括固化本体环氧树脂以将第一表面结合到第二表面。